LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Home :: News :: Downloads :: Tracker :: Discussions (cores)    

    Ethernet 10GE MAC: Home

    Details

    Name: xge_mac
    Created: 19-May-2008 08:17:33
    Updated: 07-Jun-2008 04:59:51
    CVS: browse

    Other project properties

    Category :: Communication controller
    Language :: SystemC
    Language :: Verilog
    License :: LGPL
    Standard :: Wishbone compliant core
    Development status :: Beta

    Project maintainers

  • Andre Tanguay
  • Statistics

  • view
  • Description

    The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae.

    Features

    • Interfaces
      • XGMII Interface (64-bit single clock edge)
      • POS-L3 like Interface for core logic side
      • Wishbone Interface for control
    • Inter-Frame GAP
      • Deficit Idle Count per Clause 46
    • Pause Frames
      • Received Pause Frames filtering
      • Receive Indication
    • LAN mode operation
    • Link Status
      • Local Fault Detection
      • Remote Fault Detection/Indication
    • Low-latency flow-through mode

    Status

    • (05/31/08) Verilog code completed
    • (06/06/08) SystemC and Verilog simulations completed

    Future Developments

    • RMON Statistics
    • WAN mode operation
    • Store-and-forward mode


     

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.