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Wishbone to AHB Bridge: Overview Details Name: wisbone_2_ahb Created: 06-Aug-2007 18:51:52 Updated: 07-Sep-2007 11:30:04 CVS: browse Other project properties Category :: SoC Dependencies :: Other cores Language :: Verilog Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers TooMuch Semiconductor Solutions Statistics view WISHBONE Protocol to AHB Protocol Bridge. Features AHB 2.0 compliant Wishbone B.3 compliant WISHBONE Burst NOT SUPPORTED Fully synthesisable Synchronous Verilog RTL Includes a Verilog Testbench with 9 Testcases Status RTL : Complete Testbench : Complete Document : Complete