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DragonBall/68K Wishbone interface: Overview Details Name: wbif_68k Created: 02-Dec-2002 21:04:02 Updated: 14-Feb-2004 14:17:09 CVS: browse Other project properties Category :: Other Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Richard Herveille Statistics view Description This is a Motorola DragonBall/68K to Wishbone bridge. The core translates the 16bit DragonBall/68K bus into a full featured 16bit Wishbone master bus. Features 16bit Motorola DragonBall/68K Interface 16bit full featured RevB.3 Wishbone Classic Master interface programmable address-bus size static synchronous design fully synthesisable 6LUTs in a Spartan-II, 32LCELLs in an ACEX Status Design is finished and available in Verilog for download from OpenCores CVS.