LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Overview :: News :: Downloads :: Tracker :: Discussions (cores)    

    8051 Slave to Wishbone Master Interface: Overview

    Details

    Name: wb_mcs51
    Created: 03-Mar-2008 12:38:51
    Updated: 25-Jul-2008 06:12:20
    CVS: browse

    Other project properties

    Category :: Other
    Language :: Verilog
    Phaze :: Design done
    Phaze :: FPGA proven
    Standard :: Wishbone compliant core
    Development status :: Production/Stable

    Project maintainers

  • Howard M. Harte
  • Statistics

  • view
  • Description

    Interface an 8051-compatible microcontroller with the Wishbone bus.

    Features

    • Multiplexed 8051 address/data bus to Wishbone Master
    • Very simple, very small.
    • Since 8051 has no way to add additional wait-states via an external pin, the Wishbone must be fast enough to complete the cycle in time for the 8051.

    Status

    • Tested with Silicon Labs C8051 Microcontroller and Xilinx Coolrunner2 CPLD.
    • Tested with Silicon Labs C8051 Microcontroller and Xilinx Spartan3 FPGA.
    • this core is used in the Altair32 Front Panel: www.altair32.com


     

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.