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USB 1.1 Host and Function IP core: Overview Details Name: usbhostslave Created: 30-Sep-2004 11:05:03 Updated: 17-Nov-2008 05:02:00 CVS: browse, lint reports Other project properties Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Steve Fielding Statistics view News Revision 2.0 is now available. usbhostslave now comes with separate host and slave top level modules in addition to a combined host/slave top level. So, if you only need host or slave features you get a more compact solution. New standalone usbDevice sub-project. A complete USB HID implemented entirely in logic. No processor or software required. First example project implements a USB mouse. USB PHY daughter card A USB PHY daughter card compatible with usbhostslave is available; http://www.base2designs.com/DUSB-PHY.htm Santa Cruz format daughter card that supports many development kits from Altera and Microtronix. Description USBHostSlave is a USB 1.1 Host and Function IP core. It supports full speed (12Mbps) and low speed (1.5Mbps) operation, and supports the four types of USB data transfer; control, bulk, interrupt, and isochronous transfers. USB Function has four endpoints, each with their own independent FIFO. All FIFO depths configurable via parameters. It has a 8-bit Wishbone slave bus interface. All the state machines have been designed using ActiveHDL FSM2HDL, so they are easily readable and understandable, but it is still possible to edit the Verilog RTL if so desired. Graphical state diagrams are used because they are much easier to understand than just RTL source code. Graphical state diagrams ease creation, maintenance, documentation, and re-use, of FSMs. Aldec ActiveHDL is an excellent tool for creating graphical state diagrams, only requiring a single .asf file per state machine module. This makes it easy to maintain the FSMs and incorporate them into your existing text based module hierarchy. For those who are targeting Altera FPGAS, there is a complete Quartus project for usbDevice. The project has been tested on an Altera development board, and requires a custom Santa Cruz daughter card. See downloads section for full schamatics and bill of materials. http://www.opencores.org/pdownloads.cgi/list/usbhostslave Features USB 1.1 Host and Function Full and low speed. Control, bulk, interrupt, and isochronous transfers FIFO interface FIFO depth configurable. Automatic SOF generation 8-bit Wishbone interface Status Version 2.0 is now available. Design has been tested in simulation and hardware. To do. Still need to test isochronous mode, pre-amble mode, and all host mode features related to accessing a low speed device via a hub. Synthesizable under Quartus 7.2 SP3. Uses approximately 2700 logic cells in an Altera Cyclone EP2C20. Known Issues Bus-turn-around time is compliant with low speed, but not full speed USB 1.1 specification. The USB 1.1 spec requires host or device to provide a response within 6.5 bit times in both full and low speed modes. Operating with a system clock of 48Mhz, usbhostslave currently provides a response within 1uS (12 full speed bit periods, 1.5 low speed bit times). The USB 1.1 specification takes into account the worst case system configuration of 5 cascaded hubs, and 6 maximum length cables (see figure 7-31 in USB 1.1 spec), resulting in a worst case system bus-turn-around time of 16 full speed bits. So, operating with a system clock of 48MHz, usbhostslave will be within full speed system spec for 2 cascaded hubs, and 3 maximum length cables. Increasing clock speed to 96MHz would make the core USB 1.1 compliant.