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Ultimate CRC: Overview Details Name: ultimate_crc Created: 05-May-2005 14:29:29 Updated: 22-Oct-2007 12:49:24 CVS: browse, lint reports Other project properties Category :: ECC core Language :: VHDL License :: GPL Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Geir Drange Statistics view Description Ultimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC register using XOR-logic. Although the levels of logic gets very high for wide data inputs, the throughput still benefits from this architecture, as can be seen from the synthesis page. Features Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset Status Revision 1.0 released.