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Reed Solomon Encoder: Overview Details Name: rsencoder Created: 26-Jun-2004 16:08:47 Updated: 14-May-2008 23:03:03 CVS: no files in cvs Other project properties Category :: ECC core Language :: Verilog Phaze :: Design done Development status :: Production/Stable Project maintainers Rajesh Pathak Statistics view Reed Solomon Encoder Reed Solomon Encoder synthesizable IP core compatible with G709, DVB1, DVB2 standards. Implements (n, k) code where n-k = 16 ( 8 byte error correction capable code). The verilog is written in such a way as to be easily parameterized for different values of n and k. If there is any interest for parameterization, let me know and I will create a version 2 core. Otherwise the core "as is" can be used to implement for example, a (255, 239) or (204, 188) codes. The underlying galois field is GF(2^8) with primitive polynomial, x^8+x^4+x^3+x^2+1. Features User defined generator polynomial. Allows experimentation with diferent generator polynomials for best implementation. Replacable Galois field multiplier submodule for a different primitive polynomial. Can be used for shortened codes. Achieved > 200MHZ ( = 1.6 Gbps) on Altera's Stratix FPGA. Status RTL done and design verified using testbench. Will upload soon. June 27th 2004, updated. Please click on 'Downloads' (top right on this page). June 29 2004, There was a typo in reed_solomon.v file. The output ports d0, d1, d2, d3 actually refer to q0, q1, q2, q3 (see readme.txt file). Sorry for the confusion. Corrected now.