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PLBv46 to Wishbone Bridge: Overview Details Name: plbv46_to_wb_bridge Created: 25-Jul-2008 07:20:12 Updated: 31-Jul-2008 18:54:55 CVS: browse Other project properties Category :: SoC Language :: VHDL Standard :: Wishbone compliant core Development status :: Beta Project maintainers Mark Sasten Statistics view PLBv46 to Wishbone Bridge This is a simple CoreConnect PLBv46 to Wishbone bridge that can allow Wishbone peripherals to be used on Xilinx processor designs. It conforms to the sub-set of the PLBv46 specification adopted by Xilinx in the EDK. Features PLBv46 Slave Attachment (non bursting) 32-bit interface to PLBv46 bus. 32-bit interface to Wishbone bus. Supports Handling of Retries. User can set the retry wait time. User can set number of times to retry Result of unsuccessful retry is a PLBv46 bus error ack. Handling of Bus Errors User can set how long to wait for a bus-time out (no WB ack) Results in a PLBv46 Bus Error Status New