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OpenRISC 1000: Architectural Simulator
Introduction
The aim of this project is to develop and maintain an OpenRISC 1000 architectural simulator. Or1ksim is a generic OpenRISC 1000 architecture simulator capable of emulating OpenRISC based computer systems. Or1ksim provides several unique features: - Free, open source code
- High level, fast, architecture simulation that allows early code analysis and system performance evaluation
- All major models of OpenCores peripheral and system controller cores supported
- Easy addition of new peripheral models
- Remote debugging through a network socket with the GNU Debugger (GDB)
- Support for different environments (memory configurations and sizes, OR1K processor model, configuration of peripheral devices)
Status
The latest release leading up to the 0.2.0 version is 0.2.0rc2. It may be downloaded here. To make the next release as stable as posible, we'd like as many people as possible to try out this release and report any bugs/problems that you may encounter. The current stable release of or1ksim is version 0.1.0:
- or1ksim simulates 32-bit part of the OpenRISC 1000 architecture
- or1ksim support for 64-bit part of the OpenRISC is not yet available
- Supported OpenCores peripherals: vga/lcd, uart, dma, ethernet, general purpose io, memory controller, ps2 interface (keyboard only), OCIDEC (partially)
Since the simulator is no longer only a processor simulator, but also supports peripherals, it is now used also as the ORPsoc simulator. For example the VGA peripheral can output images like the following figure, showing uClinux booting on a VGA console:
Downloading or1ksim
Source code of the current stable release (0.1.0) is availible here. You may also checkout the latetest version from cvs useing:
cvs -d :pserver:cvs@cvs.opencores.org:/home/oc/cvs -z9 co -r stable_0_1_0 -d or1ksim or1k/or1ksim
(Note that the checkout process may take awile). The brave may get a snapshot of the current development branch here.Binaries of or1ksim are not available. Building it should be straightforward.
Installation
Building or1ksim is regulary tested under RedHat 7.0 GNU/Linux only. The procedure to build and install or1ksim is the following: First get the sources useing the instructions above. Then Build and install the simulator binary:
cd or1ksim
./configure --target=or32 --prefix=/opt/or32-rtems &&
make all install
export PATH=/opt/or32-rtems/bin:$PATH
Replace /opt/or32-rtems with name of the directory where you installed (or are going to install) the rest of the toolchain (binutils/gcc/etc.).
Documentation
For booting Linux, use "or32-sim vmlinux". Check the comments in sim.cfg file and --help output for additional information.
Contributing
We are constantly looking for developers to help in the development of the simulator, though you don't need to be a highly skilled developer to do so. Many (very usefull) projects may be performed without any C programming knowledge or without an intricate knowledge of the openrisc architecture. A few items to get you started:
We are constantly short of manpower to maintain the website. If you feel you're up to doing some webdesign, don't hold back any longer! Some general ideas to get you started (by no means exhausive): Add a more indepth discussion of the simulator for the introduction, provide some more screen shots showing off some interesting features of the sim, or any other good idea you have in mind.
The simulator is sorely missing some good documentation. This is an excellent task for anyone new to or1ksim. This would involve documenting, in the form of a well narated passage (not point form!), how to get started useing or1ksim, the general pitfalls that someone new to or1ksim may take and how to avoid those, some neet examples of how to use some of the more "cool" peripherals of the sim (esp. how to make use of the ethernet peripheral), documenting the interface that is used to implement the peripherals, documenting the more arcane features of the simulator, the various execution models, branch prediction, super scaler emulation and in general what they are usefull for. If you have any questions about the above, don't hesitate to contact us on the mailing list.
- Test or1ksim on non-Linux platforms (various UNIX and Cygwin platforms) :
The developers do not have acess to every operating system out there. We would like the simulator to run on as many platforms as possible. If you are running on anything other than linux you would help us a great deal if you could periodically check if the simulator builds (and works) on your prefered platform, reporting any failures to the mailing list.
- Add additional models of OpenCores peripherals and system controllers:
- Support for running the sim on 64-bit architectures:
There are numerous places in the sim where the length of the basic C types are assumed to be a certain length (esp. the "long" type), which breaks running the simulator on 64-bit architectures.
The development version of the simulator has numerous speed otimisations already, though this is a never ending task. The uart for example needs lots of work so that uart_clock16 does not need to be called so often. The ethernet could use similar optimisations. This task generally streches quite deep into the simulator and is not concentrated into any single area.
- Support for 64-bit part of OpenRISC 1000:
This is a very big (and fun) piece of work. This does not only involve writting emulation of the 64-bit architecture. It also requires modifying the exsisting processor units such that they support 64-bit types (mmu/caches/debug unit/etc.).
If you have a suggestion that you'd like to see developed, feel free to send it to the mailing list so that may be added to the list and somebody may start working on it.
Past Contributors
These are the people who are currently not working on the or1ksim, but have contributed in significant ways in the past:
Developers
The team currently working on or1ksim:
Mailing List / Discussion Forum
To participate in the development or simply to discuss or1ksim issues and to report bugs, go to the openrisc mailing list. To subscribe to the list, follow the mailing list subscribe instructions.
Page Maintainer(s)
This web page is maintained by Jeremy Bennett and Marcus Erlandsson.
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