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I am an student,and a chinese too. I just study the verilog not a long

There are a number of ways to represent a 256 x 8 memory in Verilog.
Is this for simulation only? If it must be synthesizable, is it for an
ASIC or an FPGA? If it's for an FPGA, is it Xilinx or Altera? Do you
require a single port, or a dual port memory?

These are important questions because memory is fairly technology
dependent unless you can afford to synthesize a memory from
flip-flops. In that case, you can just do the following
(Verilog-2001).

reg [7:0] mem [0:255];

It's not very interesting, but it'll simulate just fine, and most
tools will synthesize it into a memory like object. Be warned, what
this synthesizes to will vary with tools.

As for an ARC4 core, I haven't seen any non-commercial Verilog code.
Although the algorithm is quite accessible in many places (one of
which is in the Python distribution in arc4.py) . And you might check
libtomcrypt (http://libtomcrypt.org/download.html), I know he has rc5
implemented.

On 6/2/05, zhangchao27@y... <zhangchao27@y...> wrote:
>     I am an student,and a chinese too. I just study the verilog not a long
> time . now ,I have a problem . I don`t know how to describe the 256*8
> memory in verilog . someone told me a way : 8bits address ,64columns,
> 32rows, and 7-3bits connect a 1-32bit decoder, to chose the
> row .address bits 2-0 to chose the bit. each 8 columns refer bit7 ,bit6,
> bit5 ,bit4 ,bit3,bit2 ,bit1 ,bit0 .
>     if you know someone`s work about rc4 , you can email to me, tell me
> about his work.
>     please forgive me my poor english
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