OPENCORES.ORG

Hi Armando,

Hello Sami,

         I dont know if it is possible to change that address, because what
         we have is the netlist, not the source code. Who could answer that 
question is Rudolff who
         made it.

         If different address is used, you can check with the OPB-Chipscope
         that the opb transfer is not acknoledge and the timeout signal is set.

         One solution is not to wrapp a single core but a Wishbone system 
(including
         a memory decoder with one stb and address at the input, and the 
strobes
         for the different cores at the output).

         Regards,

                 Armando

At 16:46 01/06/2005 +0200, you wrote:
>Hi Armando,
>
>I used the same solution as you, and the OPB2WB wrapper works.
>But now there is one other problem. The wrapper works only if I try to
>write to the 0x80000000 address. If I change the address range of the
>OPB2WB wrapper in EDK to in example 0x80018000, the OPB2WB does not
>work, I mean it does not assert CYC and STB signals. I tryed to change
>the PARAMETER C_BASEADDR=32'h8000_0000 C_HIGHADDR=0x800000ff to
>C_BASEADDR=0x80018000 C_HIGHADDR=0x800180ff, but it does not work.
>It works always only if I write to 0x80000000.
>This is a problem because if I use 2 WB cores, it means that I need 2
>wrappers in EDK, but they must have different address ranges,
>otherwise all data will be sent to both cores. But the wrappers works
>only in  the same address range 0x80000000 -> 0x800000ff .
>I hope I was clear in my explanation.
>Thanks for any suggestion.
>Regards
>
>Sami (secamiei)
>----- Original Message -----
>From: Armando Astarloa<jtpascua@b...>
>To:
>Date: Wed Jun  1 12:22:33 CEST 2005
>Subject: [oc] OPB2WB wrapper + SPI lite
>
> > At 14:51 16/05/2005 +0200, you wrote:
> > >EDK does not allow connection between different size buses, how
> > can I
> > >connect the WB 32 bit wrapper to the SPI 8 bit data bus ?
> >  Hello Sami,
> >  After fixing some problems i´ve used successfully the opb2wb
> > wrapper with a WB core of my own (EDK 7.1).
> >  Some of these clues are taken from the FPGA mailing list
> > 0- I´ve changed the data and address vectors of my WB core to
> > adapt it to
> > the 32 buses of the wrapper
> > 1- Download the wrapper from opencores
> > 2 - Copy the wrapper files to pcores directory
> > 3- Change the bbd file to
> >
> >
>################################################################################
>
> > ##
> > ## Copyright (C) 2000-2004 ASICS World Services, LTD.
> > ## www.asics.ws
> > ## http://www.opencores.org/mailman/listinfo/cores
> >
> >
>----------------------------------------------------------------------------------------------------------------------
>
> > Armando Astarloa Cuéllar - Universidad del Pais Vasco UPV/EHU
> > Tecnología Electrónica
> > Departamento de Electrónica y Telecomunicaciones
> > Escuela Superior de Ingenieros - Email: jtpascua at bi.ehu.es
> > Ald. de Urquijo s/n Tel.: 34 - 94 - 601 73 04
> > 48013 BILBAO (SPAIN) Fax.: 34 - 94 - 601 42 59
> > URL : ~apert
> >
> >
>----------------------------------------------------------------------------------------------------------------------
>
> >
> >
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/cores

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Armando Astarloa Cuéllar - Universidad del Pais Vasco UPV/EHU
Tecnología Electrónica
Departamento de Electrónica y Telecomunicaciones
Escuela Superior de Ingenieros - Email: jtpascua@b...
Ald. de Urquijo s/n             Tel.: 34 - 94 - 601 73 04
48013 BILBAO (SPAIN)    Fax.: 34 - 94 - 601 42 59
URL : http://det.bi.ehu.es/~apert
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