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I'm in the process of hooking up the OC WISHBONE DMA/Bridge and am having problems with the bridging or pass-through mode. I wasn't getting the data bus reflected on i/f#1 during a pass-through write cycle. I've traced back into the core VHDL and from what I can tell, the wb_dma_wb_slv module is qualifying rf_sel with the cyc_i signal from the *wrong* interface!?! rf_sel drives the mux which selects between pass-thru and dma engine data and should be qualified with the cyc_i signal from the *originating* i/f (i/f#0). To verify, I routed the i/f#0 cyc_i signal to the (currently unused) i/f#1 cyc_i signal and the data now appears OK. I also reverted to my original design and uncommented the original pt_sel logic in that module (which doesn't qualify with cyc_i) and it also worked!!! Can any one else confirm or deny this problem exists? I suspect a proper fix will require the originating cyc_i signal to be routed through the design along with the pass-thru data. Regards, -- Mark McDougall, Software Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266