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From: RT<mfoc73@d...>
Date: Wed Apr 20 19:17:33 CEST 2005
Subject: [oc] Operations within a vector
Roberto Ammendola wrote:

> A VHDL how-would-you-do-this question (if allowed here).

You'll get better answers from comp.lang.vhdl.

> Suppose you have a parametric generation of instances of a certain
> component.
> Something like:

signal MYVEC : std_logic_vector(PARAMETER downto 0);
begin
GLOBAL_B <= OR_REDUCE(MYVEC);

> inst_generator: for i in 0 to PARAMETER generate
> my_inst: component_name
> port map(
> a => a(i), -- an in signal, std_logic type
b => MYVEC(i)
> );
> end generate;