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Message
From: Mark McDougall<markm@v...>
Date: Fri Apr 1 11:20:00 CEST 2005
Subject: [oc] OCIDEC3 DMA
Mark McDougall wrote:> I'm not clear on what signal throttles a wishbone DMA master reading
> from the read FIFO during a DMA read operation?!?
> I would've expected the core to issue a wishbone RETRY if the read
> FIFO was empty, but that's not what I'm seeing.
> Anyone done DMA with OCIDEC3 before?
To answer myself, for the benefit of anyone else having these problems...
(1) the ATA device must not assert DMAREQ until *after* the core has
ack'd the wishbone cycle that starts a DMA operation on the device (eg.
DMA_READ($C9)/DMA_WRITE($CB)) otherwise the core asserts the wishbone
retry signal.
(2) The core is ready for a new transfer whenever the wishbone DMA_req
signal is asserted. The wishbone master must (DMA)ack each DWORD
transfer to/from the core.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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