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From: Mark McDougall<markm@v...>
Date: Thu Mar 31 10:09:39 CEST 2005
Subject: [oc] OCIDEC3 DMA
Hi,

I'm not clear on what signal throttles a wishbone DMA master reading
from the read FIFO during a DMA read operation?!?

I would've expected the core to issue a wishbone RETRY if the read FIFO
was empty, but that's not what I'm seeing.

Anyone done DMA with OCIDEC3 before?

TIA
Regards,

--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266