OPENCORES.ORG

Hi,

Hi.,
Already got that one - it's in the Bally code release on www.fpgaarcade.com
I have a few bug fixes from a number of people for both the 6502 and z80
cores. I have asked for CVS write permission on opencores as Daniel appears
to have vanished. I will also put up and maintain the cores on the arcade
website - when I get time.
/Mike
mikej@o...

                -- INI, IND, INIR, INDR
                -- note B is decremented AFTER being put on the bus
                MCycles <= "011";
                case to_integer(unsigned(MCycle)) is
                when 1 =>
                    TStates <= "101";
                    Set_Addr_To <= aBC;
                    Set_BusB_To <= "1010";
                    Set_BusA_To <= "0000";
                    Read_To_Reg <= '1';
                    Save_ALU <= '1';
                    ALU_Op <= "1010";
                when 2 =>
                    IORQ <= '1';
                    Set_BusB_To <= "0110";
                    Set_Addr_To <= aXY;
                when 3 =>
                    if IR(3) = '0' then
                        --IncDec_16 <= "0010";
                        IncDec_16 <= "0110";
                    else
                        --IncDec_16 <= "1010";
                        IncDec_16 <= "1110";
                    end if;
                    TStates <= "100";
                    Write <= '1';
                    if IR(4) = '1' and F(Flag_Z) = '0' then
                        MCycles <= "100";
                    end if;
                when 4 =>
                    NoRead <= '1';
                    I_BTR <= '1';
                    TStates <= "101";
                    MCycles <= "100";
                when others => null;
                end case;
when "10100011" | "10101011" | "10110011" | "10111011" =>
----- Original Message -----
From: <gutobix@g...>
To: <cores@o...>
Sent: Wednesday, March 30, 2005 1:00 PM
Subject: [oc] T80 bugfix for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR

> Hi,
> Thank you for the exellent T80 Core. I use that in the C-One Projekt.
> Now I have found a Bug and fix it.
> TobiFlex
>
> when "10100010" | "10101010" | "10110010" | "10111010" =>
> -- INI, IND, INIR, INDR
> MCycles <= "100";
> case to_integer(unsigned(MCycle)) is
> when 1 =>
> Set_Addr_To <= aBC;
> Set_BusB_To <= "1010";
> Set_BusA_To <= "0000";
> Read_To_Reg <= '1';
> Save_ALU <= '1';
> ALU_Op <= "0010";
> when 2 =>
> IORQ <= '1';
> Set_BusB_To <= "0110";
> Set_Addr_To <= aXY;
> when 3 =>
> --TobiFlex was here
> if IR(3) = '0' then
> IncDec_16 <= "0110";
> else
> IncDec_16 <= "1110";
> end if;
> TStates <= "100";
> Write <= '1';
> I_BTR <= '1';
> when 4 =>
> NoRead <= '1';
> TStates <= "101";
> when others => null;
> end case;
> when "10100011" | "10101011" | "10110011" | "10111011" =>
> -- OUTI, OUTD, OTIR, OTDR
> MCycles <= "100";
> case to_integer(unsigned(MCycle)) is
> when 1 =>
> TStates <= "101";
> Set_Addr_To <= aXY;
> Set_BusB_To <= "1010";
> Set_BusA_To <= "0000";
> Read_To_Reg <= '1';
> Save_ALU <= '1';
> ALU_Op <= "0010";
> when 2 =>
> Set_BusB_To <= "0110";
> Set_Addr_To <= aBC;
> when 3 =>
> --TobiFlex was here
> if IR(3) = '0' then
> IncDec_16 <= "0110";
> else
> IncDec_16 <= "1110";
> end if;
> IORQ <= '1';
> Write <= '1';
> I_BTR <= '1';
> when 4 =>
> NoRead <= '1';
> TStates <= "101";
> when others => null;
> end case;
> end case;
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
>