|
Message
From: Salvador Eduardo Tropea<salvador@i...>
Date: Mon Mar 28 22:51:39 CEST 2005
Subject: [oc] WB_Builder problems and fixes
Hi All!That's my first mail to this list. I couldn't find a better list at
OpenCores for that, so I hope this mail is ok.
I downloaded the wb_builder (wishbone.pl) script from CVS and I found
various bugs in the code.
One of the most important bugs is generated by the fact that the author
used gt, ge, eq, etc. for numbers. These operators are for strings and
comparissons between a string and a number using them aren't reliable.
I'm attaching an example to show how comparissons can work and also
fail. I mean: it compares strings perfectly, but you don't get what the
author was expecting. The example is called test_pl, you should rename
it to test.pl.
The code also have some problems:
1) When the data bus is 8 bits it generates a useless SEL signal, not
needed at all (it also makes the code invalid).
2) When only one master is used it generates a master selection signal.
It should be removed.
I also found the code uses CYC as the selection signal, but the Wishbone
B.3 appendix clearly states that STB should be used for that.
The attached patch fixes various bugs and adds:
1) An option to use STB instead of CYC to select the slave.
2) An option to indicate that a slave doesn't have CYC_I.
3) Generates a package containing the component declaration for the
generated entity.
4) Generates an instantiation example to cut&paste the reasult.
5) Removes the arbiter when it isn't used (cleaner).
6) An option to select the file extension (i.e. .vhdl)
7) Implements the tristate option.
8) An option to select the granularity (default is 8)
The code was tested with an 8 bits "real world" case:
Master:
1) PIC16C84 compatible core.
Slaves:
1) Character generator (VGA compatible, 40x25, 8 colors, 64 chars).
2) I2C core from OpenCores.
But I can bet the code needs more adjustments.
My main question is: Is anybody using it for real world things?
I like the idea to have a code generator for that stuff.
Regards, SET
--
Salvador Eduardo Tropea (SET). (Electronics Engineer)
Visit my home page: http://welcome.to/SetSoft or
http://www.geocities.com/SiliconValley/Vista/6552/
Alternative e-mail: set@c... set@i...
Address: Curapaligue 2124, Caseros, 3 de Febrero
Buenos Aires, (1678), ARGENTINA Phone: +(5411) 4759 0013
-------------- next part --------------
$a='1';
print "\n\$a='$a'\n";
print "\$a==1 => ".($a==1)."\n";
print "\$a eq 1 => ".($a eq 1)."\n";
print "\$a > -1 => ".($a>-1)."\n";
print "\$a gt -1 => ".($a gt -1)."\n";
$a=' 1';
print "\n\$a='$a'\n";
print "\$a==1 => ".($a==1)."\n";
print "\$a eq 1 => ".($a eq 1)."\n";
print "\$a > -1 => ".($a>-1)."\n";
print "\$a gt -1 => ".($a gt -1)."\n";
$a='10';
print "\n\$a='$a'\n";
print "\$a gt 9 => ".($a gt 9)."\n";
-------------- next part --------------
? tcedit.dst
? wb_intercon.vhd
? wishbone.defines
Index: wishbone.pl
===================================================================
RCS file: /cvsroot/anonymous/wb_builder/generator/wishbone.pl,v
retrieving revision 1.14
diff -u -r1.14 wishbone.pl
--- wishbone.pl 16 Sep 2004 07:53:22 -0000 1.14
+++ wishbone.pl 28 Mar 2005 20:30:25 -0000
@@ -1,4 +1,25 @@
#!/usr/bin/perl
+#
+# Modified by Salvador E. Tropea:
+#
+# + Option to use STB as selector instead of CYC (IMHO the rigth thing to do
+# TM).
+# + Option to avoid generating CYC_I for a particular slave.
+# + Generation of a $(intercon)_package.vhd file with the component
+# declaration.
+# + Generation of an instantiation example (in the package).
+# + Option to specify the extension (i.e. .vhdl).
+# + Implemented the "tristate" option.
+# + Option to configure the ganularity (default==8).
+#
+# * Removed some ; after }. They aren't needed.
+# * Changed le, lt, ge, gt and eq in comparissons involving numbers (these
+# operators are for strings).
+# * Moved some code to functions to make easier to maintain.
+# * Removed SEL generation when SEL isn't used.
+# * Removed arbiter when it isn't used.
+# * Removed generation of select (ss) signal when only one master is used.
+#
#use POSIX;
use Tk;
@@ -39,6 +60,8 @@
my $mux_type="andor";
my $optimize="speed";
my $priority="0";
+my $use_cyc_sel=1;
+my $granularity=8;
# keep track of implementation size
my $masters=0;
@@ -51,6 +74,7 @@
my $tgc_i=0;
my $tga_o=0;
my $tga_i=0;
+my $cyc_i=0;
# GUI FSM
my $state='WinGlobal';
@@ -97,6 +121,7 @@
$slave[$slaves]{"tgc_i"}=0;
$slave[$slaves]{"err_o"}=0;
$slave[$slaves]{"rty_o"}=0;
+ $slave[$slaves]{"cyc_i"}=1;
$slave[$slaves]{"baseadr"}="00000000";
$slave[$slaves]{"size"}="00100000";
$slave[$slaves]{"baseadr1"}="00000000";
@@ -131,27 +156,36 @@
} else {
$comment="//";
$ext=".v";
- };
- };
+ }
+ }
+
+ if ($a =~/^ext\s*=\s*(.*);?$/) {
+ $ext = $1;
+ #print "Setting extension to <$ext>\n";
+ }
if ($a =~ /^(interconnect)( *)(=)( *)(crossbarswitch|sharedbus)(;?)$/) {
- $interconnect = $5; };
+ $interconnect = $5; }
if ($a =~ /^(signal_groups)( *)(=)( *)([0-1])(;?)($*)/) {
$signal_groups = $5; };
+ if ($a =~ /^(use_cyc_sel)( *)(=)( *)([0-1])(;?)($*)/) {
+ $use_cyc_sel = $5; };
+
if ($a =~ /^(mux_type)( *)(=)( *)(mux|andor|tristate)(;?)$/) {
$mux_type = $5; };
if ($a =~ /^(optimize)( *)(=)( *)(speed|area);?$/) {
$optimize = $5; };
- if ($a =~ /^(dat_size|adr_size|tgd_bits|tga_bits|tgc_bits)( *)(=)( *)([0-9]+)(;?)($*)/) {
- if ($1 eq "dat_size"){$dat_size = $5};
- if ($1 eq "adr_size"){$adr_size = $5};
- if ($1 eq "tgd_bits"){$tgd_bits = $5};
- if ($1 eq "tga_bits"){$tga_bits = $5};
- if ($1 eq "tgc_bits"){$tgc_bits = $5};
+ if ($a =~ /^(dat_size|adr_size|tgd_bits|tga_bits|tgc_bits|granularity)( *)(=)( *)([0-9]+)(;?)($*)/) {
+ $dat_size = $5 if $1 eq 'dat_size';
+ $adr_size = $5 if $1 eq 'adr_size';
+ $tgd_bits = $5 if $1 eq 'tgd_bits';
+ $tga_bits = $5 if $1 eq 'tga_bits';
+ $tgc_bits = $5 if $1 eq 'tgc_bits';
+ $granularity = $5 if $1 eq 'granularity';
};
if ($a =~ /^(rename)(_)(tga|tgc|tgd)( *)(=)( *)([a-zA-Z_-]+)(;?)($*)/) {
@@ -169,16 +203,16 @@
until ($a =~ /^(end master)($*)/) {
if ($a =~ /^( *)(dat_size|adr_o_hi|adr_o_lo|lock_o|err_i|rty_i|tga_o|tgc_o|priority)( *)(=)( *)(0x)?([0-9a-fA-F]*)(;?)($*)/) {
$master[$masters]{"$2"}=$7;
- if (($2 eq "rty_i") && ($7 eq 1)) {
+ if (($2 eq "rty_i") && ($7 == 1)) {
$rty_i++; };
- if (($2 eq "err_i") && ($7 eq 1)) {
+ if (($2 eq "err_i") && ($7 == 1)) {
$err_i++; };
- if (($2 eq "tgc_o") && ($7 eq 1)) {
+ if (($2 eq "tgc_o") && ($7 == 1)) {
$tgc_o++; };
- if (($2 eq "tga_o") && ($7 eq 1)) {
+ if (($2 eq "tga_o") && ($7 == 1)) {
$tga_o++; };
- # priority for shared bus system
- if ($2 eq "priority") {
+ # priority for shared bus system
+ if ($2 eq "priority") {
$priority += $7; };
}; #end if
if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
@@ -197,15 +231,15 @@
};
$a = <FILE>;
until ($a =~ /^(end slave)($*)/) {
- if ($a =~ /^( *)(dat_i|dat_o|sel_i|adr_i_hi|adr_i_lo|lock_i|tga_i|tgc_i|err_o|rty_o|baseadr|size|baseadr1|size1|baseadr2|size2|baseadr3|size3)( *)(=)( *)(0x)?([0-9a-fA-F]+)(;?)($*)/) {
+ if ($a =~ /^( *)(dat_i|dat_o|sel_i|adr_i_hi|adr_i_lo|lock_i|tga_i|tgc_i|err_o|rty_o|baseadr|size|baseadr1|size1|baseadr2|size2|baseadr3|size3|cyc_i)( *)(=)( *)(0x)?([0-9a-fA-F]+)(;?)($*)/) {
$slave[$slaves]{"$2"}=$7;
- if (($2 eq "rty_o") && ($7 eq 1)) {
+ if (($2 eq "rty_o") && ($7 == 1)) {
$rty_o++; };
- if (($2 eq "err_o") && ($7 eq 1)) {
+ if (($2 eq "err_o") && ($7 == 1)) {
$err_o++; };
- if (($2 eq "tgc_i") && ($7 eq 1)) {
+ if (($2 eq "tgc_i") && ($7 == 1)) {
$tgc_i++; };
- if (($2 eq "tga_i") && ($7 eq 1)) {
+ if (($2 eq "tga_i") && ($7 == 1)) {
$tga_i++; };
}; #end if
if ($a =~ /^( *)(type)( *)(=)( *)(ro|wo|rw)(;?)($*)/) {
@@ -283,11 +317,22 @@
$frame->Label(-text => "Signal groups :")->pack(-side=>'left');
$a = $frame->Radiobutton ( -variable => \$signal_groups, -text => 'No', -value => 0)->pack( -side=>'left');
$b = $frame->Radiobutton ( -variable => \$signal_groups, -text => 'Yes', -value => 1 )->pack( -side=>'right');
+ # use_cyc_sel
+ $frame=$mw->Frame();
+ $frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
+ $frame->Label(-text => "Use CYC_O for selection :")->pack(-side=>'left');
+ $a = $frame->Radiobutton ( -variable => \$use_cyc_sel, -text => 'No', -value => 0)->pack( -side=>'left');
+ $b = $frame->Radiobutton ( -variable => \$use_cyc_sel, -text => 'Yes', -value => 1 )->pack( -side=>'right');
# dat size
$frame=$mw->Frame();
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
$frame->Label(-text => "Data bus size :")->pack(-side=>'left');
$frame->Entry(-textvariable => \$dat_size)->pack(-side=>'right');
+ # granularity
+ $frame=$mw->Frame();
+ $frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
+ $frame->Label(-text => "Granularity :")->pack(-side=>'left');
+ $frame->Entry(-textvariable => \$granularity)->pack(-side=>'right');
# adr size
$frame=$mw->Frame();
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
@@ -485,6 +530,12 @@
$frame->Label(-text => "lock_i :")->pack(-side=>'left');
$a = $frame->Radiobutton ( -variable => \$slave[$i]{"lock_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
$b = $frame->Radiobutton ( -variable => \$slave[$i]{"lock_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
+ # cyc_i
+ $frame=$mw->Frame();
+ $frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
+ $frame->Label(-text => "cyc_i :")->pack(-side=>'left');
+ $a = $frame->Radiobutton ( -variable => \$slave[$i]{"cyc_i"}, -text => 'No', -value => 0)->pack( -side=>'left');
+ $b = $frame->Radiobutton ( -variable => \$slave[$i]{"cyc_i"}, -text => 'Yes', -value => 1 )->pack( -side=>'right');
# tga_i
$frame=$mw->Frame();
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
@@ -555,7 +606,7 @@
$mw = MainWindow->new;
$mw->title ("Wishbone generator");
$frame=$mw->Frame(-label=>"Priority for shared bus system")->pack();
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
$frame=$mw->Frame();
$frame->pack(-side => 'top', -fill => 'y', -expand => 'y');
$frame->Label(-text => $master[$i]{"wbm"})->pack(-side=>'left');
@@ -578,15 +629,15 @@
$frame=$mw->Frame();
$frame->pack(-side => 'top', -fill => 'x', -expand => 'y');
$frame->Entry(-textvariable => \$tmp)->pack(-side=>'left');
- for ($j=1; $j le $slaves; $j++) {
+ for ($j=1; $j <= $slaves; $j++) {
$frame->Entry(-textvariable => \$slave[$j]{"wbs"})->pack(-side=>'left');
};
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
$frame=$mw->Frame();
$frame->pack(-side => 'top', -fill => 'x', -expand => 'y');
#$frame->Label(-text => $master[$i]{"wbm"})->pack(-side=>'left');
$frame->Entry(-textvariable => \$master[$i]{"wbm"})->pack(-side=>'left');
- for ($j=1; $j le $slaves; $j++) {
+ for ($j=1; $j <= $slaves; $j++) {
#$frame->Label(-text => $master[$i]{"priority_".($slave[$j]{"wbs"})})->pack(-side=>'left');
$frame->Entry(-textvariable => \$master[$i]{"priority_".($slave[$j]{"wbs"})})->pack(-side=>'left');
};
@@ -603,7 +654,7 @@
sub wbm_del {
my $i;
if ($_[0] != $masters) {
- for ($i=$_[0]; $i lt $masters; $i++) {
+ for ($i=$_[0]; $i < $masters; $i++) {
$master[$i]=$master[$i+1];
};
};
@@ -614,7 +665,7 @@
sub wbs_del {
my $i;
if ($_[0] != $slaves) {
- for ($i=$_[0]; $i lt $slaves; $i++) {
+ for ($i=$_[0]; $i < $slaves; $i++) {
$slave[$i]=$slave[$i+1];
};
};
@@ -726,6 +777,7 @@
printf OUTFILE "target=%s\n",$target;
printf OUTFILE "hdl=%s\n",$hdl;
printf OUTFILE "signal_groups=%s\n",$signal_groups;
+ printf OUTFILE "use_cyc_sel=%s\n",$use_cyc_sel;
printf OUTFILE "tga_bits=%s\n",$tga_bits;
printf OUTFILE "tgc_bits=%s\n",$tgc_bits;
printf OUTFILE "tgd_bits=%s\n",$tgd_bits;
@@ -735,10 +787,11 @@
printf OUTFILE "classic=%s\n",$classic;
printf OUTFILE "endofburst=%s\n",$endofburst;
printf OUTFILE "dat_size=%s\n",$dat_size;
+ printf OUTFILE "granularity=%s\n",$granularity;
printf OUTFILE "adr_size=%s\n",$adr_size;
printf OUTFILE "mux_type=%s\n",$mux_type;
printf OUTFILE "interconnect=%s\n",$interconnect;
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
printf OUTFILE "\nmaster %s\n",$master[$i]{"wbm"};
printf OUTFILE " type=%s\n",$master[$i]{"type"};
printf OUTFILE " lock_o=%s\n",$master[$i]{"lock_o"};
@@ -750,13 +803,13 @@
if ($interconnect eq "sharedbus") {
printf OUTFILE " priority=%s\n",$master[$i]{"priority"};
} else {
- for ($j=1; $j le $slaves; $j++) {
+ for ($j=1; $j <= $slaves; $j++) {
printf OUTFILE " priority_%s=%s\n",$slave[$j]{"wbs"},$master[$i]{"priority_".($slave[$j]{"wbs"})};
};
};
printf OUTFILE "end master %s\n",$master[$i]{"wbm"};
};
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
printf OUTFILE "\nslave %s\n",$slave[$i]{"wbs"};
printf OUTFILE " type=%s\n",$slave[$i]{"type"};
printf OUTFILE " adr_i_hi=%s\n",$slave[$i]{"adr_i_hi"};
@@ -765,6 +818,7 @@
printf OUTFILE " tgc_i=%s\n",$slave[$i]{"tgc_i"};
printf OUTFILE " tgd_i=%s\n",$slave[$i]{"tgd_i"};
printf OUTFILE " lock_i=%s\n",$slave[$i]{"lock_i"};
+ printf OUTFILE " cyc_i=%s\n",$slave[$i]{"cyc_i"};
printf OUTFILE " err_o=%s\n",$slave[$i]{"err_o"};
printf OUTFILE " rty_o=%s\n",$slave[$i]{"rty_o"};
printf OUTFILE " baseadr=0x%s\n",$slave[$i]{"baseadr"};
@@ -780,15 +834,17 @@
# print header
sub gen_header {
+ print OUTFILE "$comment---------------------------------------------------------------------------------------\n";
printf OUTFILE "%s Generated by PERL program wishbone.pl. Do not edit this file.\n%s\n",$comment,$comment;
printf OUTFILE "%s For defines see %s\n%s\n",$comment,$infile,$comment;
+ print OUTFILE "$comment Package: $intercon"."_package ($intercon"."_package$ext)\n$comment\n"if $hdl eq "vhdl";
$tmp=localtime(time);
printf OUTFILE "%s Generated %s\n%s\n",$comment,$tmp,$comment;
printf OUTFILE "%s Wishbone masters:\n",$comment;
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
printf OUTFILE "%s %s\n",$comment,$master[$i]{"wbm"}; };
printf OUTFILE "%s\n%s Wishbone slaves:\n",$comment,$comment;
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
printf OUTFILE "%s %s\n",$comment,$slave[$i]{"wbs"};
if ($slave[$i]{"size"} ne ffffffff) {
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr"},$slave[$i]{"size"}};
@@ -799,21 +855,21 @@
if ($slave[$i]{"size3"} ne ffffffff) {
printf OUTFILE "%s baseadr 0x%s - size 0x%s\n",$comment,$slave[$i]{"baseadr3"},$slave[$i]{"size3"}};
};
+ print OUTFILE "$comment---------------------------------------------------------------------------------------\n";
};
sub gen_vhdl_package {
- printf OUTFILE "-----------------------------------------------------------------------------------------\n";
printf OUTFILE "library IEEE;\nuse IEEE.std_logic_1164.all;\n\n";
- printf OUTFILE "package %s_package is\n\n",$intercon;
+ printf OUTFILE "package %s_int_package is\n\n",$intercon;
# records ?
- if ($signal_groups eq 1) {
- for ($i=1; $i le $masters; $i++) {
+ if ($signal_groups == 1) {
+ for ($i=1; $i <= $masters; $i++) {
# input record
printf OUTFILE "type %s_wbm_i_type is record\n",$master[$i]{"wbm"};
if ($master[$i]{"type"} =~ /(ro|rw)/) { printf OUTFILE " dat_i : std_logic_vector(%s downto 0);\n",$master[$i]{"dat_size"}-1;};
- if ($master[$i]{"err_i"} eq 1) { printf OUTFILE " err_i : std_logic;\n";};
- if ($master[$i]{"rty_i"} eq 1) { printf OUTFILE " rty_i : std_logic;\n";};
+ if ($master[$i]{"err_i"} == 1) { printf OUTFILE " err_i : std_logic;\n";};
+ if ($master[$i]{"rty_i"} == 1) { printf OUTFILE " rty_i : std_logic;\n";};
printf OUTFILE " ack_i : std_logic;\n";
printf OUTFILE "end record;\n";
# output record
@@ -821,39 +877,39 @@
if ($master[$i]{"type"} =~ /(wo|rw)/) {
printf OUTFILE " dat_o : std_logic_vector(%s downto 0);\n",$master[$i]{"dat_size"}-1;
printf OUTFILE " we_o : std_logic;\n"; };
- if ($dat_size eq 8) {
+ if ($dat_size == $granularity) {
printf OUTFILE " sel_o : std_logic;\n";
} else {
- printf OUTFILE " sel_o : std_logic_vector(%s downto 0);\n",$dat_size/8-1; };
+ printf OUTFILE " sel_o : std_logic_vector(%s downto 0);\n",$dat_size/$granularity-1; };
printf OUTFILE " adr_o : std_logic_vector(%s downto 0);\n",$adr_size-1;
- if ($master[$i]{"lock_o"} eq 1) { printf OUTFILE " lock_o : std_logic;\n";};
- if ($master[$i]{"tga_o"} eq 1) { printf OUTFILE " %s_o : std_logic_vector(%s downto 0);\n",$rename_tga, $tga_bits-1;};
- if ($master[$i]{"tgc_o"} eq 1) { printf OUTFILE " %s_o : std_logic_vector(%s downto 0);\n",$rename_tgc, $tgc_bits-1;};
+ if ($master[$i]{"lock_o"} == 1) { printf OUTFILE " lock_o : std_logic;\n";};
+ if ($master[$i]{"tga_o"} == 1) { printf OUTFILE " %s_o : std_logic_vector(%s downto 0);\n",$rename_tga, $tga_bits-1;};
+ if ($master[$i]{"tgc_o"} == 1) { printf OUTFILE " %s_o : std_logic_vector(%s downto 0);\n",$rename_tgc, $tgc_bits-1;};
printf OUTFILE " cyc_o : std_logic;\n";
printf OUTFILE " stb_o : std_logic;\n";
printf OUTFILE "end record;\n\n";
}; #end for
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
# input record
printf OUTFILE "type %s_wbs_i_type is record\n",$slave[$i]{"wbs"};
if ($slave[$i]{"type"} ne "ro") {
printf OUTFILE " dat_i : std_logic_vector(%s downto 0);\n",$slave[$i]{"dat_size"}-1;
printf OUTFILE " we_i : std_logic;\n"; };
- if ($dat_size eq 8) {
+ if ($dat_size == $granularity) {
printf OUTFILE " sel_i : std_logic;\n";
} else {
- printf OUTFILE " sel_i : std_logic_vector(%s downto 0);\n",$dat_size/8-1; };
- if ($slave[$i]{"adr_i_hi"} gt 0) { printf OUTFILE " adr_i : std_logic_vector(%s downto %s);\n",$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};};
- if ($slave[$i]{"tga_i"} eq 1) { printf OUTFILE " %s_i : std_logic_vector(%s downto 0);\n",$rename_tga,$tga_bits-1; };
- if ($slave[$i]{"tgc_i"} eq 1) { printf OUTFILE " %s_i : std_logic_vector(%s downto 0);\n",$rename_tgc,$tgc_bits-1; };
- printf OUTFILE " cyc_i : std_logic;\n";
+ printf OUTFILE " sel_i : std_logic_vector(%s downto 0);\n",$dat_size/$granularity-1; };
+ if ($slave[$i]{"adr_i_hi"} > 0) { printf OUTFILE " adr_i : std_logic_vector(%s downto %s);\n",$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};};
+ if ($slave[$i]{"tga_i"} == 1) { printf OUTFILE " %s_i : std_logic_vector(%s downto 0);\n",$rename_tga,$tga_bits-1; };
+ if ($slave[$i]{"tgc_i"} == 1) { printf OUTFILE " %s_i : std_logic_vector(%s downto 0);\n",$rename_tgc,$tgc_bits-1; };
+ printf OUTFILE " cyc_i : std_logic;\n" if $slave[$i]{'cyc_i'};
printf OUTFILE " stb_i : std_logic;\n";
printf OUTFILE "end record;\n";
# output record
printf OUTFILE "type %s_wbs_o_type is record\n",$slave[$i]{"wbs"};
if ($slave[$i]{"type"} =~ /(ro|rw)/) { printf OUTFILE " dat_o : std_logic_vector(%s downto 0);\n",$slave[$i]{"dat_size"}-1 };
- if ($slave[$i]{"rty_o"} eq 1) { printf OUTFILE " rty_o : std_logic;\n" };
- if ($slave[$i]{"err_o"} eq 1) { printf OUTFILE " err_o : std_logic;\n" };
+ if ($slave[$i]{"rty_o"} == 1) { printf OUTFILE " rty_o : std_logic;\n" };
+ if ($slave[$i]{"err_o"} == 1) { printf OUTFILE " err_o : std_logic;\n" };
printf OUTFILE " ack_o : std_logic;\n";
printf OUTFILE "end record;\n";
}; #end for
@@ -861,15 +917,16 @@
# overload of "and"
printf OUTFILE "\nfunction \"and\" (\n l : std_logic_vector;\n r : std_logic)\nreturn std_logic_vector;\n";
- printf OUTFILE "end %s_package;\n",$intercon;
- printf OUTFILE "package body %s_package is\n",$intercon;
+ printf OUTFILE "end %s_int_package;\n",$intercon;
+ printf OUTFILE "package body %s_int_package is\n",$intercon;
printf OUTFILE "\nfunction \"and\" (\n l : std_logic_vector;\n r : std_logic)\nreturn std_logic_vector is\n";
printf OUTFILE " variable result : std_logic_vector(l'range);\n";
printf OUTFILE "begin -- \"and\"\n for i in l'range loop\n result(i) := l(i) and r;\nend loop; -- i\nreturn result;\nend \"and\";\n";
- printf OUTFILE "end %s_package;\n",$intercon;
+ printf OUTFILE "end %s_int_package;\n",$intercon;
};
sub gen_trafic_ctrl {
+ return if $masters <= 1;
if ($hdl eq "vhdl") {
if ($target eq "xilinx") {
print OUTFILE <<EOP;
@@ -1017,24 +1074,31 @@
};
sub gen_entity {
+ my ($pkg)=@_;
+ my $ent;
+
# library usage
- printf OUTFILE "\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n";
- printf OUTFILE "use work.%s_package.all;\n",$intercon;
+ print OUTFILE "\nlibrary IEEE;\nuse IEEE.std_logic_1164.all;\n";
+ printf OUTFILE "use work.%s_int_package.all;\n",$intercon unless $pkg;
+ print OUTFILE "\npackage $intercon"."_package is\n" if $pkg;
+ $ent='entity' unless $pkg;
+ $ent='component' if $pkg;
+
# entity intercon
- printf OUTFILE "\nentity %s is\n port (\n",$intercon;
+ print OUTFILE "\n$ent $intercon is\n port (\n";
# records
- if ($signal_groups eq 1) {
+ if ($signal_groups == 1) {
# master port(s)
printf OUTFILE " -- wishbone master port(s)\n";
- for ($i=1; $i le $masters; $i++) {
- printf OUTFILE " -- %s\n",$master[$i]{"wbm"};
+ for ($i=1; $i <= $masters; $i++) {
+ printf OUTFILE " -- %s\n",$master[$i]{"wbm"};
printf OUTFILE " %s_wbm_i : out %s_wbm_i_type;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
printf OUTFILE " %s_wbm_o : in %s_wbm_o_type;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
}; #end for
# slave port(s)
printf OUTFILE " -- wishbone slave port(s)\n";
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
printf OUTFILE " -- %s\n",$slave[$i]{"wbs"};
printf OUTFILE " %s_wbs_i : out %s_wbs_i_type;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
printf OUTFILE " %s_wbs_o : in %s_wbs_o_type;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
@@ -1042,139 +1106,293 @@
# separate signals
} else {
printf OUTFILE " -- wishbone master port(s)\n";
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
printf OUTFILE " -- %s\n",$master[$i]{"wbm"};
if ($master[$i]{"type"} ne "wo") {
printf OUTFILE " %s_dat_i : out std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size-1; };
printf OUTFILE " %s_ack_i : out std_logic;\n",$master[$i]{"wbm"};
- if ($master[$i]{"err_i"} eq 1) {
+ if ($master[$i]{"err_i"} == 1) {
printf OUTFILE " %s_err_i : out std_logic;\n",$master[$i]{"wbm"}; };
- if ($master[$i]{"rty_i"} eq 1) {
+ if ($master[$i]{"rty_i"} == 1) {
printf OUTFILE " %s_rty_i : out std_logic;\n",$master[$i]{"wbm"}; };
if ($master[$i]{"type"} ne "ro") {
printf OUTFILE " %s_dat_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size-1;
printf OUTFILE " %s_we_o : in std_logic;\n",$master[$i]{"wbm"};
};
- if ($dat_size ge 16) {
- printf OUTFILE " %s_sel_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size/8-1; };
+ if ($dat_size>=2*$granularity) {
+ printf OUTFILE " %s_sel_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$dat_size/$granularity-1; };
printf OUTFILE " %s_adr_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$adr_size-1;
- if ($master[$i]{"tgc_o"} eq 1) {
+ if ($master[$i]{"tgc_o"} == 1) {
printf OUTFILE " %s_%s_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$rename_tgc,$tgc_bits-1; };
- if ($master[$i]{"tga_o"} eq 1) {
+ if ($master[$i]{"tga_o"} == 1) {
printf OUTFILE " %s_%s_o : in std_logic_vector(%s downto 0);\n",$master[$i]{"wbm"},$rename_tga,$tga_bits-1; };
printf OUTFILE " %s_cyc_o : in std_logic;\n",$master[$i]{"wbm"};
printf OUTFILE " %s_stb_o : in std_logic;\n",$master[$i]{"wbm"};
};
printf OUTFILE " -- wishbone slave port(s)\n";
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
printf OUTFILE " -- %s\n",$slave[$i]{"wbs"};
if ($slave[$i]{"type"} ne "wo") {
printf OUTFILE " %s_dat_o : in std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size-1; };
printf OUTFILE " %s_ack_o : in std_logic;\n",$slave[$i]{"wbs"};
- if ($slave[$i]{"err_o"} eq 1) {
+ if ($slave[$i]{"err_o"} == 1) {
printf OUTFILE " %s_err_o : in std_logic;\n",$slave[$i]{"wbs"}; };
- if ($slave[$i]{"rty_o"} eq 1) {
+ if ($slave[$i]{"rty_o"} == 1) {
printf OUTFILE " %s_rty_o : in std_logic;\n",$slave[$i]{"wbs"}; };
if ($slave[$i]{"type"} ne "ro") {
printf OUTFILE " %s_dat_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size-1;
printf OUTFILE " %s_we_i : out std_logic;\n",$slave[$i]{"wbs"};
};
- if ($dat_size ge 16) {
- printf OUTFILE " %s_sel_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size/8-1; };
+ if ($dat_size>=2*$granularity) {
+ printf OUTFILE " %s_sel_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$dat_size/$granularity-1; };
printf OUTFILE " %s_adr_i : out std_logic_vector(%s downto %s);\n",$slave[$i]{"wbs"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};
- if ($slave[$i]{"tgc_i"} eq 1) {
+ if ($slave[$i]{"tgc_i"} == 1) {
printf OUTFILE " %s_%s_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$rename_tgc,$tgc_bits-1; };
- if ($slave[$i]{"tga_i"} eq 1) {
+ if ($slave[$i]{"tga_i"} == 1) {
printf OUTFILE " %s_%s_i : out std_logic_vector(%s downto 0);\n",$slave[$i]{"wbs"},$rename_tga,$tga_bits-1; };
- printf OUTFILE " %s_cyc_i : out std_logic;\n",$slave[$i]{"wbs"};
+ printf OUTFILE " %s_cyc_i : out std_logic;\n",$slave[$i]{"wbs"} if $slave[$i]{'cyc_i'};
printf OUTFILE " %s_stb_i : out std_logic;\n",$slave[$i]{"wbs"};
};
};
# clock and reset
- printf OUTFILE " -- clock and reset\n";
- printf OUTFILE " clk : in std_logic;\n";
- printf OUTFILE " reset : in std_logic);\n";
- printf OUTFILE "end %s;\n",$intercon;
-};
+ print OUTFILE " -- clock and reset\n";
+ print OUTFILE " clk : in std_logic;\n";
+ print OUTFILE " reset : in std_logic);\n";
+ print OUTFILE "end $ent $intercon;\n";
+
+ print OUTFILE "\nend package;\n" if $pkg;
+}
+
+sub gen_asg{
+ my ($name,$sig)=@_;
+
+ print OUTFILE $name."_$sig => $name"."_$sig,\n-- ";
+}
+sub gen_example {
+ my $name;
+
+ # library usage
+ print OUTFILE "\n-- Instantiation example:\n-- library IEEE;\n-- use IEEE.std_logic_1164.all;\n";
+ printf OUTFILE "-- use work.%s_package.all;\n-- \n",$intercon;
+
+ # signals
+ printf OUTFILE "-- -- signals:\n";
+ if ($signal_groups) {
+ for ($i=1; $i <= $masters; $i++) {
+ $name=$master[$i]{'wbm'};
+ print OUTFILE "-- -- $name\n";
+ print OUTFILE "-- signal $name"."_wbm_i_type $name"."_wbm_i;\n";
+ print OUTFILE "-- signal $name"."_wbm_o_type $name"."_wbm_o;\n";
+ }
+ for ($i=1; $i <= $slaves; $i++) {
+ $name=$slave[$i]{'wbs'};
+ print OUTFILE "-- -- $name\n";
+ print OUTFILE "-- signal $name"."_wbs_i_type $name"."_wbs_i;\n";
+ print OUTFILE "-- signal $name"."_wbs_o_type $name"."_wbs_o;\n";
+ }
+ } else {
+ for ($i=1; $i <= $masters; $i++) {
+ $name=$master[$i]{'wbm'};
+ print OUTFILE "-- -- $name\n";
+ gen_sig_dec2($name,'dat_i',$dat_size) if $master[$i]{'type'} ne 'wo';
+ gen_sig_dec2($name,'ack_i');
+ gen_sig_dec2($name,'err_i') if $master[$i]{"err_i"}==1;
+ gen_sig_dec2($name,'rty_i') if $master[$i]{"rty_i"}==1;
+ if ($master[$i]{"type"} ne "ro") {
+ gen_sig_dec2($name,'dat_o',$dat_size);
+ gen_sig_dec2($name,'we_o');
+ }
+ gen_sig_dec2($name,'sel_o',$dat_size/$granularity) if $dat_size>=2*$granularity;
+ gen_sig_dec2($name,'adr_o',$adr_size);
+ gen_sig_dec2($name,$rename_tgc.'_o',$tgc_bits) if $master[$i]{"tgc_o"}==1;
+ gen_sig_dec2($name,$rename_tga.'_o',$tga_bits) if $master[$i]{"tga_o"}==1;
+ gen_sig_dec2($name,'cyc_o');
+ gen_sig_dec2($name,'stb_o');
+ }
+ for ($i=1; $i <= $slaves; $i++) {
+ $name=$slave[$i]{'wbs'};
+ print OUTFILE "-- -- $name\n";
+ gen_sig_dec2($name,'dat_o',$dat_size) if $slave[$i]{"type"} ne "wo";
+ gen_sig_dec2($name,'ack_o');
+ gen_sig_dec2($name,'err_o') if $slave[$i]{"err_o"}==1;
+ gen_sig_dec2($name,'rty_o') if $slave[$i]{"rty_o"}==1;
+ if ($slave[$i]{"type"} ne "ro") {
+ gen_sig_dec2($name,'dat_i',$dat_size);
+ gen_sig_dec2($name,'we_i');
+ }
+ gen_sig_dec2($name,'sel_i',$dat_size/$granularity) if $dat_size>=2*$granularity;
+ gen_sig_dec2($name,'adr_i',$slave[$i]{'adr_i_hi'}+1,$slave[$i]{'adr_i_lo'});
+ gen_sig_dec2($name,$rename_tgc.'_i',$tgc_bits) if $slave[$i]{"tgc_i"}==1;
+ gen_sig_dec2($name,$rename_tga.'_i',$tga_bits) if $slave[$i]{"tga_i"}==1;
+ gen_sig_dec2($name,'cyc_i') if $slave[$i]{'cyc_i'};
+ gen_sig_dec2($name,'stb_i');
+ }
+ }
+ print OUTFILE "-- \n";
+
+ # entity intercon
+ print OUTFILE "-- intercon: $intercon\n-- port map (\n";
+ # records
+ if ($signal_groups) {
+ # master port(s)
+ print OUTFILE "-- -- wishbone master port(s)\n";
+ print OUTFILE "-- ";
+ for ($i=1; $i <= $masters; $i++) {
+ $name=$master[$i]{'wbm'};
+ print OUTFILE "-- $name\n";
+ print OUTFILE "-- ";
+ gen_asg($name,'wbm_i');
+ gen_asg($name,'wbm_o');
+ } #end for
+ # slave port(s)
+ print OUTFILE "-- wishbone slave port(s)\n";
+ print OUTFILE "-- ";
+ for ($i=1; $i <= $slaves; $i++) {
+ $name=$slave[$i]{'wbs'};
+ print OUTFILE "-- $name\n";
+ print OUTFILE "-- ";
+ gen_asg($name,'wbs_i');
+ gen_asg($name,'wbs_o');
+ }
+ # separate signals
+ } else {
+ print OUTFILE "-- -- wishbone master port(s)\n";
+ for ($i=1; $i <= $masters; $i++) {
+ $name=$master[$i]{"wbm"};
+ print OUTFILE "-- -- $name\n";
+ print OUTFILE "-- ";
+ gen_asg($name,'dat_i') if $master[$i]{"type"} ne "wo";
+ gen_asg($name,'ack_i');
+ gen_asg($name,'err_i') if $master[$i]{"err_i"}==1;
+ gen_asg($name,'rty_i') if $master[$i]{"rty_i"}==1;
+ if ($master[$i]{"type"} ne "ro") {
+ gen_asg($name,'dat_o');
+ gen_asg($name,'we_o');
+ }
+ gen_asg($name,'sel_o') if $dat_size>=2*$granularity;
+ gen_asg($name,'adr_o');
+ gen_asg($name,$rename_tgc.'_o') if $master[$i]{"tgc_o"}==1;
+ gen_asg($name,$rename_tga.'_o') if $master[$i]{"tga_o"}==1;
+ gen_asg($name,'cyc_o');
+ gen_asg($name,'stb_o');
+ }
+ print OUTFILE "-- wishbone slave port(s)\n";
+ print OUTFILE "-- ";
+ for ($i=1; $i <= $slaves; $i++) {
+ $name=$slave[$i]{'wbs'};
+ print OUTFILE "-- $name\n";
+ print OUTFILE "-- ";
+ gen_asg($name,'dat_o') if $slave[$i]{"type"} ne "wo";
+ gen_asg($name,'ack_o');
+ gen_asg($name,'err_o') if $slave[$i]{"err_o"}==1;
+ gen_asg($name,'rty_o') if $slave[$i]{"rty_o"}==1;
+ if ($slave[$i]{"type"} ne "ro") {
+ gen_asg($name,'dat_i');
+ gen_asg($name,'we_i');
+ }
+ gen_asg($name,'sel_i') if $dat_size>=2*$granularity;
+ gen_asg($name,'adr_i');
+ gen_asg($name,$rename_tgc.'_i') if $slave[$i]{"tgc_i"}==1;
+ gen_asg($name,$rename_tga.'_i') if $slave[$i]{"tga_i"}==1;
+ gen_asg($name,'cyc_i') if $slave[$i]{'cyc_i'};
+ gen_asg($name,'stb_i');
+ }
+ }
+ # clock and reset
+ print OUTFILE "-- clock and reset\n";
+ print OUTFILE "-- clk => clk, reset => reset);\n";
+}
+
+
+sub gen_sig_dec {
+ if ($_[1] > 0) {
+ printf OUTFILE " signal %s : std_logic_vector(%s downto %s);\n",$_[0],$_[1]-1,$_[2];
+ } else {
+ printf OUTFILE " signal %s : std_logic;\n",$_[0];
+ }
+}
+
+sub gen_sig_dec2 {
+ my $indent=substr(' ',1,6-length($_[1]));
+ if ($_[2] > 0) {
+ printf OUTFILE "-- signal %s_%s%s: std_logic_vector(%d downto %d);\n",
+ $_[0],$_[1],$indent,$_[2]-1,$_[3];
+ } else {
+ printf OUTFILE "-- signal %s_%s%s: std_logic;\n",$_[0],$_[1],$indent;
+ }
+}
# generate signals for remapping (for records)
sub gen_sig_remap {
- sub gen_sig_dec {
- if ($_[1] gt 0) {
- printf OUTFILE " signal %s : std_logic_vector(%s downto %s);\n",$_[0],$_[1]-1,$_[2];
- } else {
- printf OUTFILE " signal %s : std_logic;\n",$_[0];
- };
- };
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
if ($master[$i]{"type"} ne "wo") {
gen_sig_dec($master[$i]{"wbm"}.'_dat_i',$dat_size,0); };
gen_sig_dec($master[$i]{"wbm"}.'_ack_i');
- if ($master[$i]{"err_i"} eq 1) {
+ if ($master[$i]{"err_i"} == 1) {
gen_sig_dec($master[$i]{"wbm"}.'_err_i'); };
- if ($master[$i]{"rty_i"} eq 1) {
+ if ($master[$i]{"rty_i"} == 1) {
gen_sig_dec($master[$i]{"wbm"}.'_rty_i') };
if ($master[$i]{"type"} ne "ro") {
gen_sig_dec($master[$i]{"wbm"}.'_dat_o',$dat_size,0);
gen_sig_dec($master[$i]{"wbm"}.'_we_o ');
};
- if ($dat_size > 8) {
- gen_sig_dec($master[$i]{"wbm"}.'_sel_o',$dat_size/8,0); };
+ if ($dat_size > $granularity) {
+ gen_sig_dec($master[$i]{"wbm"}.'_sel_o',$dat_size/$granularity,0); };
gen_sig_dec($master[$i]{"wbm"}.'_adr_o',$adr_size,0);
- if ($master[$i]{"tga_o"} eq 1) {
+ if ($master[$i]{"tga_o"} == 1) {
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tga.'_o',$tga_bits,0); };
- if ($master[$i]{"tgc_o"} eq 1) {
+ if ($master[$i]{"tgc_o"} == 1) {
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tgc.'_o',$tgc_bits,0); };
- if ($master[$i]{"tgd_o"} eq 1) {
+ if ($master[$i]{"tgd_o"} == 1) {
gen_sig_dec($master[$i]{"wbm"}.'_'.$rename_tgd.'_o',$tgd_bits,0); };
gen_sig_dec($master[$i]{"wbm"}.'_cyc_o');
gen_sig_dec($master[$i]{"wbm"}.'_stb_o');
};
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
if ($slave[$i]{"type"} ne "wo") {
gen_sig_dec($slave[$i]{"wbs"}.'_dat_o',$dat_size,0); };
gen_sig_dec($slave[$i]{"wbs"}.'_ack_o');
- if ($slave[$i]{"err_o"} eq 1) {
+ if ($slave[$i]{"err_o"} == 1) {
gen_sig_dec($slave[$i]{"wbs"}.'_err_o'); };
- if ($slave[$i]{"rty_o"} eq 1) {
+ if ($slave[$i]{"rty_o"} == 1) {
gen_sig_dec($slave[$i]{"wbs"}.'_rty_o'); };
if ($slave[$i]{"type"} ne "ro") {
gen_sig_dec($slave[$i]{"wbs"}.'_dat_i',$dat_size,0);
gen_sig_dec($slave[$i]{"wbs"}.'_we_i ');
};
- if ($dat_size > 8) {
- gen_sig_dec($slave[$i]{"wbs"}.'_sel_i',$dat_size/8,0); };
+ if ($dat_size > $granularity) {
+ gen_sig_dec($slave[$i]{"wbs"}.'_sel_i',$dat_size/$granularity,0); };
gen_sig_dec($slave[$i]{"wbs"}.'_adr_i',$slave[$i]{"adr_i_hi"}+1,$slave[$i]{"adr_i_lo"});
- if ($slave[$i]{"tga_i"} eq 1) {
+ if ($slave[$i]{"tga_i"} == 1) {
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tga.'_i',$tga_bits,0); };
- if ($slave[$i]{"tgc_i"} eq 1) {
+ if ($slave[$i]{"tgc_i"} == 1) {
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tgc.'_i',$tgc_bits,0); };
- if ($slave[$i]{"tgd_i"} eq 1) {
+ if ($slave[$i]{"tgd_i"} == 1) {
gen_sig_dec($slave[$i]{"wbs"}.'_'.$rename_tgd.'_i',$tgd_bits,0); };
- gen_sig_dec($slave[$i]{"wbs"}.'_cyc_i');
+ gen_sig_dec($slave[$i]{"wbs"}.'_cyc_i') if $slave[$i]{'cyc_i'};
gen_sig_dec($slave[$i]{"wbs"}.'_stb_i');
};
};
sub gen_global_signals {
# single master
- if ($masters eq 1) {
+ if ($masters == 1) {
# slave select for generation of stb_i to slaves
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
printf OUTFILE " signal %s_ss : std_logic; -- slave select\n",$slave[$i]{"wbs"}; };
# shared bus
} elsif ($interconnect eq "sharedbus") {
# bus grant
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
printf OUTFILE " signal %s_bg : std_logic; -- bus grant\n",$master[$i]{"wbm"}; };
# slave select for generation of stb_i to slaves
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
printf OUTFILE " signal %s_ss : std_logic; -- slave select\n",$slave[$i]{"wbs"}; };
# crossbarswitch
} else {
- for ($i=1; $i le $masters; $i++) {
- for ($j=1; $j le $slaves; $j++) {
+ for ($i=1; $i <= $masters; $i++) {
+ for ($j=1; $j <= $slaves; $j++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE " signal %s_%s_ss : std_logic; -- slave select\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
printf OUTFILE " signal %s_%s_bg : std_logic; -- bus grant\n",$master[$i]{"wbm"},$slave[$j]{"wbs"};
@@ -1186,25 +1404,26 @@
sub gen_arbiter {
# out: wbm_bg (bus grant)
- if ($masters eq 1) {
+ if ($masters == 1) {
# ack_i
# cyc_i
# printf OUTFILE "%s_bg <= %s_cyc_o;\n",$master[1]{"wbm"},$master[1]{"wbm"};
+ # printf OUTFILE "%s_bg <= '1';\n",$master[1]{"wbm"};
# sharedbus
} elsif ($interconnect eq "sharedbus") {
printf OUTFILE "arbiter_sharedbus: block\n";
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
printf OUTFILE " signal %s_bg_1, %s_bg_2, %s_bg_q : std_logic;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"}; };
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
printf OUTFILE " signal %s_trafic_ctrl_limit : std_logic;\n",$master[$i]{"wbm"}; };
printf OUTFILE " signal ack, ce, idle :std_logic;\n";
printf OUTFILE "begin -- arbiter\n";
printf OUTFILE "ack <= %s_ack_o",$slave[1]{"wbs"};
- for ($i=2; $i le $slaves; $i++) {
+ for ($i=2; $i <= $slaves; $i++) {
printf OUTFILE " or %s_ack_o",$slave[$i]{"wbs"}; };
printf OUTFILE ";\n";
# instantiate trafic_supervision(s)
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
printf OUTFILE "\ntrafic_supervision_%s : entity work.trafic_supervision\n",$i;
printf OUTFILE "generic map(\n";
printf OUTFILE " priority => %s,\n",$master[$i]{"priority"};
@@ -1218,50 +1437,50 @@
# _bg_q
# bg eq 1 => set
# end of cycle => reset
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
printf OUTFILE "\nprocess(clk,reset)\nbegin\nif reset='1' then\n";
printf OUTFILE " %s_bg_q <= '0';\n",$master[$i]{"wbm"};
printf OUTFILE "elsif clk'event and clk='1' then\n";
printf OUTFILE "if %s_bg_q='0' then\n",$master[$i]{"wbm"};
printf OUTFILE " %s_bg_q <= %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
printf OUTFILE "elsif ack='1'";
- if ($master[$i]{"tgc_o"} eq 1) {
+ if ($master[$i]{"tgc_o"} == 1) {
printf OUTFILE " and (%s_%s_o=\"%s\" or %s_%s_o=\"%s\")",$master[$i]{"wbm"},$rename_tgc,$classic,$master[$i]{"wbm"},$rename_tgc,$endofburst; };
printf OUTFILE " then\n %s_bg_q <= '0';\nend if;\nend if;\nend process;\n",$master[$i]{"wbm"};
}; # end for
# _bg
printf OUTFILE "\nidle <= '1' when %s_bg_q='0'",$master[1]{"wbm"};
- for ($i=2; $i le $masters; $i++) {
+ for ($i=2; $i <= $masters; $i++) {
printf OUTFILE " and %s_bg_q='0'",$master[$i]{"wbm"}; };
printf OUTFILE " else '0';\n";
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_trafic_ctrl_limit='0' else '0';\n",$master[1]{"wbm"},$master[1]{"wbm"},$master[1]{"wbm"};
$depend = $master[1]{"wbm"}."_bg_1='0'";
- for ($i=2; $i le $masters; $i++) {
+ for ($i=2; $i <= $masters; $i++) {
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_trafic_ctrl_limit='0' and (%s) else '0';\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$depend;
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
};
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' else '0';\n",$master[1]{"wbm"},$depend,$master[1]{"wbm"};
$depend = $depend." and ".$master[1]{"wbm"}."_bg_2='0'";
- for ($i=2; $i le $masters; $i++) {
+ for ($i=2; $i <= $masters; $i++) {
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"};
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_2='0'";
};
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
printf OUTFILE "%s_bg <= %s_bg_q or %s_bg_1 or %s_bg_2;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"}; };
# ce
printf OUTFILE "ce <= %s_cyc_o",$master[1]{"wbm"};
- for ($i=2; $i le $masters; $i++) {
+ for ($i=2; $i <= $masters; $i++) {
printf OUTFILE " or %s_cyc_o",$master[$i]{"wbm"}; };
printf OUTFILE " when idle='1' else '0';\n\n";
# thats it
printf OUTFILE "end block arbiter_sharedbus;\n\n";
# interconnect crossbarswitch
} else {
- for ($j=1; $j le $slaves; $j++) {
+ for ($j=1; $j <= $slaves; $j++) {
# single master ?
$tmp=0;
- for ($l=1; $l le $masters; $l++) {
+ for ($l=1; $l <= $masters; $l++) {
if ($master[$l]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
$only_master = $l;
$tmp++;
@@ -1271,7 +1490,7 @@
printf OUTFILE "%s_%s_bg <= %s_%s_ss and %s_cyc_o;\n",$master[$only_master]{"wbm"},$slave[$j]{"wbs"},$master[$only_master]{"wbm"},$slave[$j]{"wbs"},$master[$only_master]{"wbm"};
} else {
printf OUTFILE "arbiter_%s : block\n",$slave[$j]{"wbs"};
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE " signal %s_bg, %s_bg_1, %s_bg_2, %s_bg_q : std_logic;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"};
printf OUTFILE " signal %s_trafic_limit : std_logic;\n",$master[$i]{"wbm"};
@@ -1283,9 +1502,9 @@
# instantiate trafic_supervision(s)
# calc tot priority per slave
$priority = 0;
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
$priority += $master[$i]{("priority_".($slave[$j]{"wbs"}))}; };
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE "\ntrafic_supervision_%s : entity work.trafic_supervision\n",$i;
printf OUTFILE "generic map(\n";
@@ -1302,7 +1521,7 @@
# _bg_q
# bg eq 1 => set
# end of cycle => reset
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE "\nprocess(clk,reset)\nbegin\nif reset='1' then\n";
printf OUTFILE " %s_bg_q <= '0';\n",$master[$i]{"wbm"};
@@ -1310,39 +1529,39 @@
printf OUTFILE "if %s_bg_q='0' then\n",$master[$i]{"wbm"};
printf OUTFILE " %s_bg_q <= %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
printf OUTFILE "elsif ack='1'";
- if ($master[$i]{"tgc_o"} eq 1) {
+ if ($master[$i]{"tgc_o"} == 1) {
printf OUTFILE " and (%s_%s_o=\"%s\" or %s_%s_o=\"%s\")",$master[$i]{"wbm"},$rename_tgc,$classic,$master[$i]{"wbm"},$rename_tgc,$endofburst; };
printf OUTFILE " then\n %s_bg_q <= '0';\nend if;\nend if;\nend process;\n",$master[$i]{"wbm"};
};
}; # end for
# _bg
- $depend = "";
+ $depend = "";
$tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} ne 0) {$tmp++};
printf OUTFILE "\nidle <= '1' when %s_bg_q='0'",$master[$tmp]{"wbm"};
- for ($i=$tmp+1; $i le $masters; $i++) {
+ for ($i=$tmp+1; $i <= $masters; $i++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE " and %s_bg_q='0'",$master[$i]{"wbm"};
};
};
printf OUTFILE " else '0';\n";
printf OUTFILE "%s_bg_1 <= '1' when idle='1' and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"},$master[$tmp]{"wbm"};
- $depend = $master[$tmp]{"wbm"}."_bg_1='0'",;
- for ($i=$tmp+1; $i le $masters; $i++) {
+ $depend = $master[$tmp]{"wbm"}."_bg_1='0'",;
+ for ($i=$tmp+1; $i <= $masters; $i++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
- printf OUTFILE "%s_bg_1 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};;
- $depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
+ printf OUTFILE "%s_bg_1 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' and %s_trafic_limit='0' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};;
+ $depend = $depend." and ".$master[$i]{"wbm"}."_bg_1='0'";
};
};
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' else '0';\n",$master[$tmp]{"wbm"},$depend,$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"};
$depend = $depend." and ".$master[$tmp]{"wbm"}."_bg_2='0'";
$tmp1 = $tmp;
- for ($i=$tmp+1; $i le $masters; $i++) {
+ for ($i=$tmp+1; $i <= $masters; $i++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE "%s_bg_2 <= '1' when idle='1' and (%s) and %s_cyc_o='1' and %s_%s_ss='1' else '0';\n",$master[$i]{"wbm"},$depend,$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
$depend = $depend." and ".$master[$i]{"wbm"}."_bg_2='0'";
};
};
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE "%s_bg <= %s_bg_q or %s_bg_1 or %s_bg_2;\n",$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"},$master[$i]{"wbm"};
};
@@ -1350,14 +1569,14 @@
# ce
$tmp=1; until ($master[$tmp]{("priority_".($slave[$j]{"wbs"}))} ne 0) {$tmp++};
printf OUTFILE "ce <= (%s_cyc_o and %s_%s_ss)",$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$j]{"wbs"};
- for ($i=$tmp+1; $i le $masters; $i++) {
+ for ($i=$tmp+1; $i <= $masters; $i++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE " or (%s_cyc_o and %s_%s_ss)",$master[$i]{"wbm"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
};
};
printf OUTFILE " when idle='1' else '0';\n";
# global bg
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE "%s_%s_bg <= %s_bg;\n",$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"};
};
@@ -1369,22 +1588,24 @@
};
sub gen_adr_decoder{
- printf OUTFILE "decoder:block\n";
+ printf OUTFILE "\ndecoder: block\n";
if ($interconnect eq "sharedbus") {
printf OUTFILE " signal adr : std_logic_vector(%s downto 0);\n",$adr_size-1;
printf OUTFILE "begin\n";
# adr
- printf OUTFILE "adr <= (%s_adr_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
- if ($masters gt 1){
- for ($i=2; $i le $masters; $i++) {
+ if ($masters > 1){
+ printf OUTFILE "adr <= (%s_adr_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
+ for ($i=2; $i <= $masters; $i++) {
printf OUTFILE " or (%s_adr_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
- };
+ } else {
+ printf OUTFILE "adr <= %s_adr_o",$master[1]{"wbm"};
+ }
printf OUTFILE ";\n";
# slave select
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
printf OUTFILE "%s_ss <= '1' when adr(%s downto %s)=\"",$slave[$i]{"wbs"}, $adr_size-1,log(hex($slave[$i]{"size"}))/log(2);
$slave[$i]{"baseadr"}=hex($slave[$i]{"baseadr"});
- for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size"}))/log(2)); $j--) {
+ for ($j=$adr_size-1; $j >= (log(hex($slave[$i]{"size"}))/log(2)); $j--) {
if (($slave[$i]{"baseadr"}) >= (2**$j)) {
$slave[$i]{"baseadr"} -= 2**$j;
printf OUTFILE "1";
@@ -1397,13 +1618,13 @@
if ($slave[$i]{"size1"} ne "ffffffff") {
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size1"}))/log(2);
$slave[$i]{"baseadr1"}=hex($slave[$i]{"baseadr1"});
- for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size1"}))/log(2)); $j--) {
- if (($slave[$i]{"baseadr1"}) >= (2**$j)) {
+ for ($j=$adr_size-1; $j >= (log(hex($slave[$i]{"size1"}))/log(2)); $j--) {
+ if (($slave[$i]{"baseadr1"}) >= (2**$j)) {
$slave[$i]{"baseadr1"} -= 2**$j;
printf OUTFILE "1";
- } else {
- printf OUTFILE "0";
- }; # end if
+ } else {
+ printf OUTFILE "0";
+ }; # end if
}; # end for
printf OUTFILE "\"";
};
@@ -1411,13 +1632,13 @@
if ($slave[$i]{"size2"} ne "ffffffff") {
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size2"}))/log(2);
$slave[$i]{"baseadr2"}=hex($slave[$i]{"baseadr2"});
- for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size2"}))/log(2)); $j--) {
- if (($slave[$i]{"baseadr2"}) >= (2**$j)) {
- $slave[$i]{"baseadr2"} -= 2**$j;
- printf OUTFILE "1";
- } else {
- printf OUTFILE "0";
- };
+ for ($j=$adr_size-1; $j >= (log(hex($slave[$i]{"size2"}))/log(2)); $j--) {
+ if (($slave[$i]{"baseadr2"}) >= (2**$j)) {
+ $slave[$i]{"baseadr2"} -= 2**$j;
+ printf OUTFILE "1";
+ } else {
+ printf OUTFILE "0";
+ };
};
printf OUTFILE "\"";
};
@@ -1425,33 +1646,33 @@
if ($slave[$i]{"size3"} ne "ffffffff") {
printf OUTFILE " else\n'1' when adr(%s downto %s)=\"",$adr_size-1,log(hex($slave[$i]{"size3"}))/log(2);
$slave[$i]{"baseadr3"}=hex($slave[$i]{"baseadr3"});
- for ($j=$adr_size-1; $j ge (log(hex($slave[$i]{"size3"}))/log(2)); $j--) {
- if (($slave[$i]{"baseadr3"}) >= (2**$j)) {
+ for ($j=$adr_size-1; $j >= (log(hex($slave[$i]{"size3"}))/log(2)); $j--) {
+ if (($slave[$i]{"baseadr3"}) >= (2**$j)) {
$slave[$i]{"baseadr3"} -= 2**$j;
- printf OUTFILE "1";
- } else {
- printf OUTFILE "0";
- };
+ printf OUTFILE "1";
+ } else {
+ printf OUTFILE "0";
+ };
};
printf OUTFILE "\"";
};
- printf OUTFILE " else\n'0';\n";
+ printf OUTFILE " else '0';\n";
# adr to slaves
};
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
printf OUTFILE "%s_adr_i <= adr(%s downto %s);\n",$slave[$i]{"wbs"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"}; };
# crossbar switch
} else {
printf OUTFILE "begin\n";
# master_slave_ss
# $j=0;
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
$slave[$j]{"baseadr"}=hex($slave[$j]{"baseadr"});
- for ($j=1; $j le $slaves; $j++) {
+ for ($j=1; $j <= $slaves; $j++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE "%s_%s_ss <= '1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$slave[$j]{"wbs"},$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size"}))/log(2);
$tmp=hex($slave[$j]{"baseadr"});
- for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size"}))/log(2)); $k--) {
+ for ($k=$adr_size-1; $k >= (log(hex($slave[$j]{"size"}))/log(2)); $k--) {
if ($tmp >= (2**$k)) {
$tmp -= 2**$k;
printf OUTFILE "1";
@@ -1464,13 +1685,13 @@
if ($slave[$j]{"size1"} ne "ffffffff") {
printf OUTFILE " else\n'1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size1"}))/log(2);
$tmp=hex($slave[$j]{"baseadr1"});
- for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size1"}))/log(2)); $k--) {
- if ($tmp >= (2**$k)) {
- $tmp -= 2**$k;
- printf OUTFILE "1";
- } else {
- printf OUTFILE "0";
- };
+ for ($k=$adr_size-1; $k >= (log(hex($slave[$j]{"size1"}))/log(2)); $k--) {
+ if ($tmp >= (2**$k)) {
+ $tmp -= 2**$k;
+ printf OUTFILE "1";
+ } else {
+ printf OUTFILE "0";
+ };
};
printf OUTFILE "\"";
};
@@ -1478,36 +1699,36 @@
if ($slave[$j]{"size2"} ne "ffffffff") {
printf OUTFILE " else\n'1' when %s_adr_o(%s downto %s)=\"",$master[$i]{"wbm"},$adr_size-1,log(hex($slave[$j]{"size2"}))/log(2);
$tmp=hex($slave[$j]{"baseadr2"});
- for ($k=$adr_size-1; $k ge (log(hex($slave[$j]{"size2"}))/log(2)); $k--) {
- if ($tmp >= (2**$k)) {
- $tmp -= 2**$k;
- printf OUTFILE "1";
- } else {
- printf OUTFILE "0";
- };
+ for ($k=$adr_size-1; $k >= (log(hex($slave[$j]{"size2"}))/log(2)); $k--) {
+ if ($tmp >= (2**$k)) {
+ $tmp -= 2**$k;
+ printf OUTFILE "1";
+ } else {
+ printf OUTFILE "0";
+ };
};
printf OUTFILE "\"";
};
- printf OUTFILE " else \n'0';\n";
+ printf OUTFILE " else '0';\n";
}; #if
};
};
# _adr_o
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
# mux ?
$tmp=0;
- for ($l=1; $l le $masters; $l++) {
+ for ($l=1; $l <= $masters; $l++) {
if ($master[$l]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
$tmp++;
};
};
- if ($tmp eq 1) {
+ if ($tmp == 1) {
$k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$k++};
printf OUTFILE "%s_adr_i <= %s_adr_o(%s downto %s);\n",$slave[$i]{"wbs"},$master[$k]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"};
} else {
$k=1; until ($master[$k]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$k++};
printf OUTFILE "%s_adr_i <= (%s_adr_o(%s downto %s) and %s_%s_bg)",$slave[$i]{"wbs"},$master[$k]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"},$master[$k]{"wbm"},$slave[$i]{"wbs"};
- for ($j=$k+1; $j le $masters; $j++) {
+ for ($j=$k+1; $j <= $masters; $j++) {
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
printf OUTFILE " or (%s_adr_o(%s downto %s) and %s_%s_bg)",$master[$j]{"wbm"},$slave[$i]{"adr_i_hi"},$slave[$i]{"adr_i_lo"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
};
@@ -1519,201 +1740,297 @@
printf OUTFILE "end block decoder;\n\n";
};
+sub get_master{
+ my $ret=$master[$_[0]]{'wbm'};
+ $ret.='_'.$_[1] if $_[1];
+ return $ret;
+}
+
+sub get_slave{
+ my $ret=$slave[$_[0]]{'wbs'};
+ $ret.='_'.$_[1] if $_[1];
+ return $ret;
+}
+
+sub gen_common_ms{
+ my ($sig_name,$exclude,$include) = @_;
+ my ($i, $inc_masters, $first);
+
+ $inc_masters = 0;
+ $first = 0;
+ for ($i=1; $i <= $masters; $i++) {
+ if ($master[$i]{"type"} ne $exclude) {
+ $inc_masters++;
+ $first = $i if $first==0;
+ }
+ }
+ #print "$sig_name: \$exclude=\"$exclude\" \$first=$first \$inc_masters=$inc_masters\n";
+ return if $inc_masters==0;
+ print OUTFILE "-- $sig_name Master -> Slave\n";
+ if ($inc_masters > 1) {
+ print OUTFILE $sig_name.'_m2s <= ('.get_master($first,$sig_name).
+ '_o and '.get_master($first).'_bg)';
+ for ($i=$first+1; $i <= $masters; $i++) {
+ print OUTFILE ' or ('.get_master($i,$sig_name).'_o and '.
+ get_master($i).'_bg)'; }
+ } else {
+ print OUTFILE $sig_name.'_m2s <= '.get_master($first,$sig_name).'_o';
+ }
+ print OUTFILE ";\n";
+ for ($i=1; $i <= $slaves; $i++) {
+ print OUTFILE get_slave($i,$sig_name).'_i <= '.$sig_name."_m2s;\n"
+ if ($slave[$i]{"type"} ne $exclude) && (!$include || $slave[$i]{$include.'_i'}!=0); }
+}
+
+sub gen_andor_bus{
+ my ($i, $inc_slaves, $first);
+
+ $inc_slaves = 0;
+ $first = 0;
+ for ($i=1; $i <= $slaves; $i++) {
+ if ($slave[$i]{"type"} ne 'wo') {
+ $inc_slaves++;
+ $first = $i if $first==0;
+ }
+ }
+ return if $inc_slaves==0;
+ print OUTFILE "-- dat Slave -> Master [and/or]\n";
+
+ print OUTFILE 'dat_s2m <= ('.get_slave($first,'dat').'_o and '.
+ get_slave($first).'_ss)';
+ if ($inc_slaves > 1) {
+ for ($i=$first+1; $i <= $slaves; $i++) {
+ print OUTFILE ' or ('.get_slave($i,'dat').'_o and '.
+ get_slave($first).'_ss)' if ($slave[$i]{"type"} ne 'wo');
+ }
+ }
+ print OUTFILE ";\n";
+ for ($i=1; $i <= $masters; $i++) {
+ if ($master[$i]{"type"} ne 'wo') {
+ print OUTFILE get_master($i,'dat')."_i <= dat_s2m;\n";
+ }
+ }
+}
+
+sub gen_hiz_bus{
+ my ($i, $inc_slaves, $first);
+
+ $inc_slaves = 0;
+ $first = 0;
+ for ($i=1; $i <= $slaves; $i++) {
+ if ($slave[$i]{"type"} ne 'wo') {
+ $inc_slaves++;
+ $first = $i if $first==0;
+ }
+ }
+ return if $inc_slaves==0;
+ print OUTFILE "-- dat Slave -> Master [three state]\n";
+
+ if ($inc_slaves==1) {
+ print OUTFILE " -- Simplified because we have only one readable Slave\n";
+ print OUTFILE 'dat_s2m <= '.get_slave($first,'dat')."_o;\n";
+ } else {
+ for ($i=1; $i <= $slaves; $i++) {
+ print OUTFILE 'dat_s2m <= '.get_slave($i,'dat').'_o when '.
+ get_slave($i)."_ss='1' else (others => 'Z');\n"
+ if ($slave[$i]{"type"} ne 'wo');
+ }
+ }
+ for ($i=1; $i <= $masters; $i++) {
+ print OUTFILE get_master($i,'dat')."_i <= dat_s2m;\n"
+ if ($master[$i]{"type"} ne 'wo');
+ }
+}
+
+sub gen_common_sm{
+ my $sig_name = $_[0];
+ my $i;
+
+ print OUTFILE "-- $sig_name Slave -> Master\n";
+ # At least 1 slave exists
+ print OUTFILE $sig_name.'_s2m <= '.get_slave(1,$sig_name).'_o';
+ for ($i=2; $i <= $slaves; $i++) {
+ printf OUTFILE ' or '.get_slave($i,$sig_name).'_o'; }
+ print OUTFILE ";\n";
+ if ($masters > 1) {
+ for ($i=1; $i <= $masters; $i++) {
+ print OUTFILE get_master($i,$sig_name).'_i <= '.$sig_name.
+ '_s2m and '.get_master($i)."_bg;\n"; };
+ } else {
+ print OUTFILE get_master(1,$sig_name).'_i <= '.$sig_name."_s2m;\n";
+ }
+}
+
+sub gen_sel_ms{
+ my $sig_name = $_[0];
+ my $i;
+
+ print OUTFILE "-- $sig_name Master -> Slave [Selection]\n";
+ if ($masters > 1) {
+ print OUTFILE $sig_name.'_m2s <= ('.get_master(1,$sig_name).'_o and '.
+ get_master(1).'_bg)';
+ for ($i=2; $i <= $masters; $i++) {
+ print OUTFILE ' or ('.get_master($i,$sig_name).'_o and '.
+ get_master(1).'_bg)'; }
+ } else {
+ print OUTFILE $sig_name.'_m2s <= '.get_master(1,$sig_name).'_o';
+ }
+ print OUTFILE ";\n";
+ for ($i=1; $i <= $slaves; $i++) {
+ print OUTFILE get_slave($i,$sig_name).'_i <= '.get_slave($i).
+ '_ss and '.$sig_name."_m2s;\n"; }
+}
+
+sub gen_optional{
+ my ($sig_name,$n_o,$n_i)=@_;
+ my $i,$j;
+
+ return if ($n_o == 0) && ($n_i == 0);
+ print OUTFILE "-- $sig_name Slave -> Master [Optional]\n";
+ if (($n_o == 0) && ($n_i > 0)) {
+ for ($i=1; $i <= $masters; $i++) {
+ if ($master[$i]{$sig_name.'_i'} == 1) {
+ print OUTFILE get_master($i,$sig_name)."_i <= '0';\n";
+ }
+ }
+ } elsif (($n_o == 1) && ($n_i > 0)) {
+ $i=1; until ($slave[$i]{$sig_name.'_o'} == 1) {$i++};
+ for ($j=1; $j <= $masters; $j++) {
+ if ($master[$j]{$sig_name.'_i'} == 1) {
+ print OUTFILE get_master($j,$sig_name).'_i <= '.
+ get_slave($i,$sig_name)."_o;\n";
+ }
+ }
+ } elsif (($n_o > 1) && ($n_i > 0)) {
+ $i=1; until ($slave[$i]{$sig_name.'_o'} == 1) {$i++};
+ print OUTFILE $sig_name.' <= '.get_slave($i,$sig_name).'_o';
+ for ($j=$i+1; $j <= $slaves; $j++) {
+ if ($slave[$j]{$sig_name.'_o'} == 1) {
+ print OUTFILE ' or '.get_slave($j,$sig_name).'_o';
+ }
+ }
+ print OUTFILE ";\n";
+ for ($i=1; $i <= $masters; $i++) {
+ if ($master[$i]{$sig_name.'_i'} == 1) {
+ print OUTFILE get_master($i,$sig_name).'_i <= '.$sig_name.";\n";
+ }
+ }
+ }
+}
+
sub gen_muxshb{
+ my $i;
+
printf OUTFILE "mux: block\n";
- printf OUTFILE " signal cyc, stb, we, ack : std_logic;\n";
- if (($rty_i gt 0) && ($rty_o gt 1)) {
- printf OUTFILE " signal rty : std_logic;\n"; };
- if (($err_i gt 0) && ($err_o gt 1)) {
- printf OUTFILE " signal err : std_logic;\n"; };
- if ($dat_size eq 8) {
- printf OUTFILE " signal sel : std_logic;\n";
+
+ # Count how many slaves have CYC_I
+ for ($cyc_i=0,$i=1; $i<=$slaves; $i++) {
+ $cyc_i++ if $slave[$i]{'cyc_i'}>0; }
+ die "All slaves must use CYC_I when this signal is used for selection\n"
+ if $use_cyc_sel && ($cyc_i!=$slaves);
+
+ print OUTFILE " signal stb_m2s, we_m2s, ack_s2m : std_logic;\n";
+ print OUTFILE " signal cyc_m2s : std_logic;\n" if $cyc_i>0;
+ if (($rty_i > 0) && ($rty_o > 1)) {
+ print OUTFILE " signal rty : std_logic;\n"; };
+ if (($err_i > 0) && ($err_o > 1)) {
+ print OUTFILE " signal err : std_logic;\n"; };
+ if ($dat_size == $granularity) {
+ # Why?!!
+ #printf OUTFILE " signal sel : std_logic;\n";
} else {
- printf OUTFILE " signal sel : std_logic_vector(%s downto 0);\n",$dat_size/8-1;
+ printf OUTFILE " signal sel : std_logic_vector(%s downto 0);\n",$dat_size/$granularity-1;
};
printf OUTFILE " signal dat_m2s, dat_s2m : std_logic_vector(%s downto 0);\n",$dat_size-1;
- if (($tgc_o gt 0) && ($tgc_i gt 0)) {
+ if (($tgc_o > 0) && ($tgc_i > 0)) {
printf OUTFILE " signal tgc : std_logic_vector(%s downto 0);\n",$tgc_bits-1; };
- if (($tga_o gt 0) && ($tga_i gt 0)) {
+ if (($tga_o > 0) && ($tga_i > 0)) {
printf OUTFILE " signal tga : std_logic_vector(%s downto 0);\n",$tga_bits-1; };
printf OUTFILE "begin\n";
# cyc
- printf OUTFILE "cyc <= (%s_cyc_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
- if ($masters gt 1) {
- for ($i=2; $i le $masters; $i++) {
- printf OUTFILE " or (%s_cyc_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
- };
- printf OUTFILE ";\n";
- for ($i=1; $i le $slaves; $i++) {
- printf OUTFILE "%s_cyc_i <= %s_ss and cyc;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
+ if ($use_cyc_sel) {
+ gen_sel_ms('cyc');
+ } else {
+ gen_common_ms('cyc','','cyc') if $cyc_i>0;
+ }
# stb
- printf OUTFILE "stb <= (%s_stb_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
- if ($masters gt 1) {
- for ($i=2; $i le $masters; $i++) {
- printf OUTFILE " or (%s_stb_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
- };
- printf OUTFILE ";\n";
- for ($i=1; $i le $slaves; $i++) {
- printf OUTFILE "%s_stb_i <= stb;\n",$slave[$i]{"wbs"}; };
+ if ($use_cyc_sel) {
+ gen_common_ms('stb');
+ } else {
+ gen_sel_ms('stb');
+ }
# we
- $i=1; until ($master[$i]{"type"} ne "ro") {$i++};
- printf OUTFILE "we <= (%s_we_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
- if ($i lt $masters) {
- for ($j=$i+1; $j le $masters; $j++) {
- if ($master[$j]{"type"} ne "ro") {
- printf OUTFILE " or (%s_we_o and %s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"};
- };
- };
- };
- printf OUTFILE ";\n";
- for ($i=1; $i le $slaves; $i++) {
- if ($slave[$i]{"type"} ne "ro") {
- printf OUTFILE "%s_we_i <= we;\n",$slave[$i]{"wbs"};
- };
- };
+ gen_common_ms('we','ro');
# ack
- printf OUTFILE "ack <= %s_ack_o",$slave[1]{"wbs"};
- for ($i=2; $i le $slaves; $i++) {
- printf OUTFILE " or %s_ack_o",$slave[$i]{"wbs"}; };
- printf OUTFILE ";\n";
- for ($i=1; $i le $masters; $i++) {
- printf OUTFILE "%s_ack_i <= ack and %s_bg;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
+ gen_common_sm('ack');
# rty
- if (($rty_o eq 0) && ($rty_i gt 0)) {
- for ($i=1; $i le $masters; $i++) {
- if ($master[$i]{"rty_i"} eq 1) {
- printf OUTFILE "%s_rty_i <= '0';\n",$master[$i]{"wbm"};
- };
- };
- } elsif (($rty_o eq 1) && ($rty_i gt 0)) {
- $i=1; until ($slave[$i]{"rty_o"} eq 1) {$i++};
- for ($j=1; $j le $masters; $j++) {
- if ($master[$j]{"rty_i"} eq 1) {
- printf OUTFILE "%s_rty_i <= %s_rty_o;\n",$master[$j]{"wbm"},$slave[$i]{"wbs"};
- };
- };
- } elsif (($rty_o gt 1) && ($rty_i gt 0)) {
- $i=1; until ($slave[$i]{"rty_o"} eq 1) {$i++};
- printf OUTFILE "rty <= %s_rty_o",$slave[$i]{"wbs"};
- for ($j=$i+1; $j le $slaves; $j++) {
- if ($slave[$j]{"rty_o"} eq 1) {
- printf OUTFILE " or %s_rty_o",$slave[$j]{"wbs"};
- };
- };
- printf OUTFILE ";\n";
- for ($i=1; $i le $masters; $i++) {
- if ($master[$i]{"rty_i"} eq 1) {
- printf OUTFILE "%s_rty_i <= rty;\n",$master[$i]{"wbm"};
- };
- };
- };
+ gen_optional('rty',$rty_o,$rty_i);
# err
- if (($err_o eq 0) && ($err_i gt 0)) {
- for ($i=1; $i le $masters; $i++) {
- if ($master[$i]{"err_i"} eq 1) {
- printf OUTFILE "%s_err_i <= '0';\n",$master[$i]{"wbm"};
- };
- };
- } elsif (($err_o eq 1) && ($err_i gt 0)) {
- $i=1; until ($slave[$i]{"err_o"} eq 1) {$i++};
- for ($j=1; $j le $masters; $j++) {
- if ($master[$j]{"err_i"} eq 1) {
- printf OUTFILE "%s_err_i <= %s_err_o;\n",$master[$j]{"wbm"},$slave[$i]{"wbs"};
- };
- };
- } elsif (($err_o gt 1) && ($err_i gt 0)) {
- $i=1; until ($slave[$i]{"err_o"} eq 1) {$i++};
- printf OUTFILE "err <= %s_err_o",$slave[$i]{"wbs"};
- for ($j=$i+1; $j le $slaves; $j++) {
- if ($slave[$j]{"err_o"} eq 1) {
- printf OUTFILE " or %s_err_o",$slave[$j]{"wbs"};
+ gen_optional('err',$err_o,$err_i);
+ # sel
+ if ($dat_size >= 2*$granularity) {
+ if ($masters > 1) {
+ printf OUTFILE "sel <= (%s_sel_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
+ for ($i=2; $i <= $masters; $i++) {
+ printf OUTFILE " or (%s_sel_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
};
- };
+ } else {
+ printf OUTFILE "sel <= %s_sel_o",$master[1]{"wbm"};
+ }
printf OUTFILE ";\n";
- for ($i=1; $i le $masters; $i++) {
- if ($master[$i]{"err_i"} eq 1) {
- printf OUTFILE "%s_err_i <= err;\n",$master[$i]{"wbm"};
- };
- };
- };
- # sel
- printf OUTFILE "sel <= (%s_sel_o and %s_bg)",$master[1]{"wbm"},$master[1]{"wbm"};
- if ($masters gt 1) {
- for ($i=2; $i le $masters; $i++) {
- printf OUTFILE " or (%s_sel_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
- };
- };
- printf OUTFILE ";\n";
- for ($i=1; $i le $slaves; $i++) {
- printf OUTFILE "%s_sel_i <= sel;\n",$slave[$i]{"wbs"}; };
+ for ($i=1; $i <= $slaves; $i++) {
+ printf OUTFILE "%s_sel_i <= sel;\n",$slave[$i]{"wbs"}; };
+ }
# data m2s
- $i=1; until ($master[$i]{"type"} ne "ro") {$i++};
- printf OUTFILE "dat_m2s <= (%s_dat_o and %s_bg)",$master[$i]{"wbm"},$master[$i]{"wbm"};
- if ($i lt $masters) {
- for ($j=$i+1; $j le $masters; $j++) {
- printf OUTFILE " or (%s_dat_o and %s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"};
- };
- };
- printf OUTFILE ";\n";
- for ($i=1; $i le $slaves; $i++) {
- if ($slave[$i]{"type"} ne "ro") {
- printf OUTFILE "%s_dat_i <= dat_m2s;\n",$slave[$i]{"wbs"};
- };
- };
+ gen_common_ms('dat','ro');
# data s2m
- $i=1; until ($slave[$i]{"type"} ne "wo") {$i++};
- printf OUTFILE "dat_s2m <= (%s_dat_o and %s_ss)",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
- if ($i lt $slaves) {
- for ($j=$i+1; $j le $slaves; $j++) {
- printf OUTFILE " or (%s_dat_o and %s_ss)",$slave[$j]{"wbs"},$slave[$j]{"wbs"};
- };
- };
- printf OUTFILE ";\n";
- for ($i=1; $i le $masters; $i++) {
- if ($master[$i]{"type"} ne "wo") {
- printf OUTFILE "%s_dat_i <= dat_s2m;\n",$master[$i]{"wbm"};
- };
- };
+ if ($mux_type eq "andor") {
+ gen_andor_bus();
+ } elsif ($mux_type eq "tristate") {
+ gen_hiz_bus();
+ } else {
+ die "Unsuported mux_type='$mux_type'\n";
+ }
# tgc
- if (($tgc_o eq 0) && ($tgc_i gt 0)) {
- for ($i=1; $i le $slaves; $i++) {
- if ($slave[$i]{"tgc_i"} eq 1) {
+ if (($tgc_o == 0) && ($tgc_i > 0)) {
+ for ($i=1; $i <= $slaves; $i++) {
+ if ($slave[$i]{"tgc_i"} == 1) {
printf OUTFILE "%s_%s_i <= %s;\n",$slave[$i]{"wbs"},$rename_tgc,$classic;
};
};
- } elsif (($tgc_o gt 0) && ($tgc_i gt 0)) {
- $i=1; until ($master[$i]{"tgc_o"} eq 1) {$i++};
+ } elsif (($tgc_o > 0) && ($tgc_i > 0)) {
+ $i=1; until ($master[$i]{"tgc_o"} == 1) {$i++};
printf OUTFILE "tgc <= (%s_%s_o and %s_bg)",$master[$i]{"wbm"},$rename_tgc,$master[$i]{"wbm"};
- for ($j=$i+1; $j le $masters; $j++) {
- if ($master[$j]{"tgc_o"} eq 1) {
+ for ($j=$i+1; $j <= $masters; $j++) {
+ if ($master[$j]{"tgc_o"} == 1) {
printf OUTFILE " or (%s_%s_o and %s_bg)",$master[$j]{"wbm"},$rename_tgc,$master[$j]{"wbm"};
};
};
printf OUTFILE ";\n";
- for ($i=1; $i le $slaves; $i++) {
- if ($slave[$i]{"tgc_i"} eq 1) {
+ for ($i=1; $i <= $slaves; $i++) {
+ if ($slave[$i]{"tgc_i"} == 1) {
printf OUTFILE "%s_%s_i <= tgc;\n",$slave[$i]{"wbs"},$rename_tgc,$slave[$i]{"wbs"};
};
};
};
# tga
- if (($tga_o eq 0) && ($tga_i gt 0)) {
- for ($i=1; $i le $slaves; $i++) {
- if ($slave[$i]{"tga_i"} eq 1) {
+ if (($tga_o == 0) && ($tga_i > 0)) {
+ for ($i=1; $i <= $slaves; $i++) {
+ if ($slave[$i]{"tga_i"} == 1) {
printf OUTFILE "%s_%s_i <= (others=>'0');\n",$slave[$i]{"wbs"},$rename_tga;
};
};
- } elsif (($tga_o gt 0) && ($tga_i gt 0)) {
- $i=1; until ($master[$i]{"tga_o"} eq 1) {$i++};
+ } elsif (($tga_o > 0) && ($tga_i > 0)) {
+ $i=1; until ($master[$i]{"tga_o"} == 1) {$i++};
printf OUTFILE "tga <= (%s_%s_o and %s_bg)",$master[$i]{"wbm"},$rename_tga,$master[$i]{"wbm"};
- for ($j=$i+1; $j le $masters; $j++) {
- if ($master[$j]{"tga_o"} eq 1) {
+ for ($j=$i+1; $j <= $masters; $j++) {
+ if ($master[$j]{"tga_o"} == 1) {
printf OUTFILE " or (%s_%s_o and %s_bg)",$master[$j]{"wbm"},$rename_tga,$master[$j]{"wbm"};
};
};
printf OUTFILE ";\n";
- for ($i=1; $i le $slaves; $i++) {
- if ($slave[$i]{"tga_i"} eq 1) {
+ for ($i=1; $i <= $slaves; $i++) {
+ if ($slave[$i]{"tga_i"} == 1) {
printf OUTFILE "%s_%s_i <= tga;\n",$slave[$i]{"wbs"},$rename_tga,$slave[$i]{"wbs"};
};
};
@@ -1725,10 +2042,10 @@
sub gen_muxcbs{
# cyc
printf OUTFILE "-- cyc_i(s)\n";
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
printf OUTFILE "%s_cyc_i <= (%s_cyc_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
- for ($j=$tmp+1; $j le $masters; $j++) {
+ for ($j=$tmp+1; $j <= $masters; $j++) {
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
printf OUTFILE " or (%s_cyc_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
};
@@ -1737,10 +2054,10 @@
};
# stb
printf OUTFILE "-- stb_i(s)\n";
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
printf OUTFILE "%s_stb_i <= (%s_stb_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
- for ($j=$tmp+1; $j le $masters; $j++) {
+ for ($j=$tmp+1; $j <= $masters; $j++) {
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
printf OUTFILE " or (%s_stb_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
};
@@ -1749,11 +2066,11 @@
};
# we
printf OUTFILE "-- we_i(s)\n";
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
if ($slave[$i]{"type"} ne "ro") {
$tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
printf OUTFILE "%s_we_i <= (%s_we_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
- for ($j=$tmp+1; $j le $masters; $j++) {
+ for ($j=$tmp+1; $j <= $masters; $j++) {
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
printf OUTFILE " or (%s_we_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
};
@@ -1763,10 +2080,10 @@
};
# ack
printf OUTFILE "-- ack_i(s)\n";
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
printf OUTFILE "%s_ack_i <= (%s_ack_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
- for ($j=$tmp+1; $j le $slaves; $j++) {
+ for ($j=$tmp+1; $j <= $slaves; $j++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE " or (%s_ack_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
};
@@ -1775,20 +2092,20 @@
};
# rty
printf OUTFILE "-- rty_i(s)\n";
- for ($i=1; $i le $masters; $i++) {
- if ($master[$i]{"rty_i"} eq 1) {
+ for ($i=1; $i <= $masters; $i++) {
+ if ($master[$i]{"rty_i"} == 1) {
$rty_o=0;
- for ($j=1; $j le $masters; $j++) {
- if (($slave[$j]{"rty_o"} eq 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
+ for ($j=1; $j <= $masters; $j++) {
+ if (($slave[$j]{"rty_o"} == 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
$rty_o+=1;
};
};
- if ($rty_o eq 0) {
+ if ($rty_o == 0) {
printf OUTFILE "%s_rty_i <= '0';\n",$master[$i]{"wbm"};
} else {
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
printf OUTFILE "%s_rty_i <= (%s_rty_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
- for ($j=$tmp+1; $j le $slaves; $j++) {
+ for ($j=$tmp+1; $j <= $slaves; $j++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE " or (%s_rty_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
};
@@ -1799,20 +2116,20 @@
};
# err
printf OUTFILE "-- err_i(s)\n";
- for ($i=1; $i le $masters; $i++) {
- if ($master[$i]{"err_i"} eq 1) {
+ for ($i=1; $i <= $masters; $i++) {
+ if ($master[$i]{"err_i"} == 1) {
$err_o=0;
- for ($j=1; $j le $masters; $j++) {
- if (($slave[$j]{"err_o"} eq 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
+ for ($j=1; $j <= $masters; $j++) {
+ if (($slave[$j]{"err_o"} == 1) && ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0)) {
$err_o+=1;
};
};
- if ($err_o eq 0) {
+ if ($err_o == 0) {
printf OUTFILE "%s_err_i <= '0';\n",$master[$i]{"wbm"};
} else {
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
printf OUTFILE "%s_err_i <= (%s_err_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
- for ($j=$tmp+1; $j le $slaves; $j++) {
+ for ($j=$tmp+1; $j <= $slaves; $j++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
printf OUTFILE " or (%s_err_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
};
@@ -1823,11 +2140,11 @@
};
# sel
printf OUTFILE "-- sel_i(s)\n";
- for ($i=1; $i le $slaves; $i++) {
- if ($dat_size >= 16) {
+ for ($i=1; $i <= $slaves; $i++) {
+ if ($dat_size >= 2*$granularity) {
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++};
printf OUTFILE "%s_sel_i <= (%s_sel_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
- for ($j=$tmp+1; $j le $masters; $j++) {
+ for ($j=$tmp+1; $j <= $masters; $j++) {
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
printf OUTFILE " or (%s_sel_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
};
@@ -1837,21 +2154,21 @@
};
# dat
printf OUTFILE "-- slave dat_i(s)\n";
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
if ($slave[$i]{"type"} ne "ro") {
$tmp=0;
- for ($j=1; $j le $masters; $j++) {
+ for ($j=1; $j <= $masters; $j++) {
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
$tmp+=1;
};
};
- if ($tmp eq 1) {
+ if ($tmp == 1) {
$j=1; until (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {$j++};
printf OUTFILE "%s_dat_i <= %s_dat_o;\n",$slave[$i]{"wbs"},$master[$j]{"wbm"};
} elsif ($tmp >= 1) {
$tmp=1; until (($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$tmp]{"type"} ne "ro")) {$tmp++};
printf OUTFILE "%s_dat_i <= (%s_dat_o and %s_%s_bg)",$slave[$i]{"wbs"},$master[$tmp]{"wbm"},$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
- for ($j=$tmp+1; $j le $masters; $j++) {
+ for ($j=$tmp+1; $j <= $masters; $j++) {
if (($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) && ($master[$j]{"type"} ne "ro")) {
printf OUTFILE " or (%s_dat_o and %s_%s_bg)",$master[$j]{"wbm"},$master[$j]{"wbm"},$slave[$i]{"wbs"};
};
@@ -1861,21 +2178,21 @@
};
};
printf OUTFILE "-- master dat_i(s)\n";
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
if ($master[$i]{"type"} ne "wo") {
$tmp=0;
- for ($j=1; $j le $slaves; $j++) {
+ for ($j=1; $j <= $slaves; $j++) {
if ($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) {
$tmp+=1;
};
};
- if ($tmp eq 1) {
+ if ($tmp == 1) {
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
printf OUTFILE "%s_dat_i <= %s_dat_o",$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
} else {
$tmp=1; until ($master[$i]{("priority_".($slave[$tmp]{"wbs"}))} ne 0) {$tmp++};
printf OUTFILE "%s_dat_i <= (%s_dat_o and %s_%s_bg)",$master[$i]{"wbm"},$slave[$tmp]{"wbs"},$master[$i]{"wbm"},$slave[$tmp]{"wbs"};
- for ($j=$tmp+1; $j le $slaves; $j++) {
+ for ($j=$tmp+1; $j <= $slaves; $j++) {
if (($master[$i]{("priority_".($slave[$j]{"wbs"}))} ne 0) && ($master[$i]{"type"} ne "wo")) {
printf OUTFILE " or (%s_dat_o and %s_%s_bg)",$slave[$j]{"wbs"},$master[$i]{"wbm"},$slave[$j]{"wbs"};
};
@@ -1886,29 +2203,29 @@
};
# tgc
printf OUTFILE "-- tgc_i\n";
- for ($i=1; $i le $slaves; $i++) {
- if ($slave[$i]{"tgc_i"} eq 1) {
+ for ($i=1; $i <= $slaves; $i++) {
+ if ($slave[$i]{"tgc_i"} == 1) {
$tmp=0;
- for ($j=1; $j le $masters; $j++) {
+ for ($j=1; $j <= $masters; $j++) {
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
$tmp+=1;
};
};
- if ($tmp eq 1) {
+ if ($tmp == 1) {
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
printf OUTFILE "%s_%s_i <= %s_%s_o",$slave[$i]{"wbs"},$rename_tgc,$master[$tmp]{"wbm"},$rename_tgc;
} else {
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
printf OUTFILE "%s_%s_i <= (%s_%s_o and %s_%s_bg)",$slave[$i]{"wbs"},$rename_tgc,$master[$tmp]{"wbm"},$rename_tgc,$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
- for ($j=$tmp+1; $j le $masters; $j++) {
+ for ($j=$tmp+1; $j <= $masters; $j++) {
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
- if ($master[$j]{"tga_o"} eq 1) {
+ if ($master[$j]{"tga_o"} == 1) {
printf OUTFILE " or (%s_%s_o and %s_%s_bg)",$master[$j]{"wbm"},$rename_tgc,$master[$j]{"wbm"},$slave[$i]{"wbs"};
- } else {
- if ($classic ne "000") {
- printf OUTFILE " or \"%s\"",$classic;
- };
- };
+ } else {
+ if ($classic ne "000") {
+ printf OUTFILE " or \"%s\"",$classic;
+ };
+ };
};
};
@@ -1918,25 +2235,25 @@
};
# tga
printf OUTFILE "-- tga_i\n";
- for ($i=1; $i le $slaves; $i++) {
- if ($slave[$i]{"tga_i"} eq 1) {
+ for ($i=1; $i <= $slaves; $i++) {
+ if ($slave[$i]{"tga_i"} == 1) {
$tmp=0;
- for ($j=1; $j le $masters; $j++) {
+ for ($j=1; $j <= $masters; $j++) {
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
$tmp+=1;
};
};
- if ($tmp eq 1) {
+ if ($tmp == 1) {
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
printf OUTFILE "%s_%s_i <= %s_%s_o",$slave[$i]{"wbs"},$rename_tga,$master[$tmp]{"wbm"},$rename_tga;
} else {
$tmp=1; until ($master[$tmp]{("priority_".($slave[$i]{"wbs"}))} ne 0) {$tmp++;};
printf OUTFILE "%s_%s_i <= (%s_%s_o and %s_%s_bg)",$slave[$i]{"wbs"},$rename_tga,$master[$tmp]{"wbm"},$rename_tga,$master[$tmp]{"wbm"},$slave[$i]{"wbs"};
- for ($j=$tmp+1; $j le $masters; $j++) {
+ for ($j=$tmp+1; $j <= $masters; $j++) {
if ($master[$j]{("priority_".($slave[$i]{"wbs"}))} ne 0) {
- if ($master[$j]{"tga_o"} eq 1) {
+ if ($master[$j]{"tga_o"} == 1) {
printf OUTFILE " or (%s_%s_o and %s_%s_bg)",$master[$j]{"wbm"},$rename_tga,$master[$j]{"wbm"},$slave[$i]{"wbs"};
- };
+ };
};
};
};
@@ -1946,13 +2263,13 @@
};
sub gen_remap{
- for ($i=1; $i le $masters; $i++) {
+ for ($i=1; $i <= $masters; $i++) {
if ($master[$i]{"type"} ne "wo") {
printf OUTFILE "%s_wbm_i.dat_i <= %s_dat_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
printf OUTFILE "%s_wbm_i.ack_i <= %s_ack_i ;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
- if ($master[$i]{"err_i"} eq 1) {
+ if ($master[$i]{"err_i"} == 1) {
printf OUTFILE "%s_wbm_i.err_i <= %s_err_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
- if ($master[$i]{"rty_i"} eq 1) {
+ if ($master[$i]{"rty_i"} == 1) {
printf OUTFILE "%s_wbm_i.rty_i <= %s_rty_i;\n",$master[$i]{"wbm"},$master[$i]{"wbm"}; };
if ($master[$i]{"type"} ne "ro") {
printf OUTFILE "%s_dat_o <= %s_wbm_o.dat_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
@@ -1960,20 +2277,20 @@
};
printf OUTFILE "%s_sel_o <= %s_wbm_o.sel_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
printf OUTFILE "%s_adr_o <= %s_wbm_o.adr_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
- if ($master[$i]{"tgc_o"} eq 1) {
+ if ($master[$i]{"tgc_o"} == 1) {
printf OUTFILE "%s_%s_o <= %s_wbm_o.%s_o;\n",$master[$i]{"wbm"},$rename_tgc,$master[$i]{"wbm"},$rename_tgc; };
- if ($master[$i]{"tga_o"} eq 1) {
+ if ($master[$i]{"tga_o"} == 1) {
printf OUTFILE "%s_%s_o <= %s_wbm_o.%s_o;\n",$master[$i]{"wbm"},$rename_tga,$master[$i]{"wbm"},$rename_tga; };
printf OUTFILE "%s_cyc_o <= %s_wbm_o.cyc_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
printf OUTFILE "%s_stb_o <= %s_wbm_o.stb_o;\n",$master[$i]{"wbm"},$master[$i]{"wbm"};
};
- for ($i=1; $i le $slaves; $i++) {
+ for ($i=1; $i <= $slaves; $i++) {
if ($slave[$i]{"type"} ne "wo") {
printf OUTFILE "%s_dat_o <= %s_wbs_o.dat_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
printf OUTFILE "%s_ack_o <= %s_wbs_o.ack_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
- if ($slave[$i]{"err_o"} eq 1) {
+ if ($slave[$i]{"err_o"} == 1) {
printf OUTFILE "%s_err_o <= %s_wbs_o.err_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
- if ($slave[$i]{"rty_o"} eq 1) {
+ if ($slave[$i]{"rty_o"} == 1) {
printf OUTFILE "%s_rty_o <= %s_wbs_o.rty_o;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; };
if ($slave[$i]{"type"} ne "ro") {
printf OUTFILE "%s_wbs_i.dat_i <= %s_dat_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
@@ -1981,11 +2298,12 @@
};
printf OUTFILE "%s_wbs_i.sel_i <= %s_sel_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
printf OUTFILE "%s_wbs_i.adr_i <= %s_adr_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
- if ($slave[$i]{"tgc_i"} eq 1) {
+ if ($slave[$i]{"tgc_i"} == 1) {
printf OUTFILE "%s_wbs_i.%s_i <= %s_%s_i;\n",$slave[$i]{"wbs"},$rename_tgc,$slave[$i]{"wbs"},$rename_tgc; };
- if ($slave[$i]{"tga_i"} eq 1) {
+ if ($slave[$i]{"tga_i"} == 1) {
printf OUTFILE "%s_wbs_i.%s_i <= %s_%s_i;\n",$slave[$i]{"wbs"},$rename_tga,$slave[$i]{"wbs"},$rename_tga; };
- printf OUTFILE "%s_wbs_i.cyc_i <= %s_cyc_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
+ if ($slave[$i]{'cyc_i'}) {
+ printf OUTFILE "%s_wbs_i.cyc_i <= %s_cyc_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"}; }
printf OUTFILE "%s_wbs_i.stb_i <= %s_stb_i;\n",$slave[$i]{"wbs"},$slave[$i]{"wbs"};
};
};
@@ -2007,15 +2325,15 @@
# main
open(OUTFILE,">$outfile$ext") or die "could not write to $outfile$ext";
-gen_header;
if ($hdl eq 'vhdl') {
+ gen_header;
gen_vhdl_package;
gen_trafic_ctrl;
gen_entity;
- printf OUTFILE "architecture rtl of %s is\n",$intercon;
+ print OUTFILE "architecture rtl of $intercon is\n",;
if ($signal_groups == 1) { gen_sig_remap; };
gen_global_signals;
- printf OUTFILE "begin -- rtl\n";
+ print OUTFILE "begin -- rtl\n";
gen_arbiter;
gen_adr_decoder;
if ($interconnect eq 'sharedbus') {
@@ -2024,8 +2342,15 @@
gen_muxcbs;
};
if ($signal_groups == 1) { gen_remap; };
- printf OUTFILE "end rtl;";
-} else {
+ print OUTFILE "end rtl;";
+
+ close(OUTFILE);
+ open(OUTFILE,">$outfile"."_package$ext") or die "could not write to $outfile"."_package$ext";
+ gen_entity(1);
+ gen_example;
+ close(OUTFILE);
+} else {
+ die "Unimplemented HDL language: $hdl\n";
};
close(OUTFILE);
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