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Message
From: Mark McDougall<markm@v...>
Date: Tue Mar 22 06:38:00 CET 2005
Subject: [oc] OCIDEC3 testbench
I've just started looking at the abovementioned core and its associated
testbench.
Out-of-the-box it fails fairly early on in the piece... I've managed to
find that problem...
The main test look was calling wb_wr4 with a delay value of 0 for the
1st iteration of the test. In this case stb is being de-asserted and
reasserted immediately and the cycle never completes.
I simply changed the starting value of the loop to '1' but I'm wondering
why it failed in the first place?
iotest1 now completes with 0 errors.
iotest2 fails immediately but I'm yet to look into it.
Regards,
--
Mark McDougall, Software Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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