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Message
From: tryapurva at yahoo.co.in<tryapurva@y...>
Date: Tue Mar 15 07:08:52 CET 2005
Subject: [oc] Bank-switched memory design
hi every1,
I am an undergraduate student and am designing a system in which
a bank-switched memory is required. However, I am facing some problems
implementing this in Verilog as I have to have simultaneous read/write
i.e. while one bank is being written with data, the other bank must be
read. I have written a code for this, but don't know if it is correct.
Will someone help me out?
--------------------------------------------------Code----------------------------------------------------
module Memory(clk,MemAddr1,MemAddr2,InData,Oen,RdWr0_1,RdWr0_2,OutData);
input clk,RdWr0_1,RdWr0_2,Oen;
input [5:0] MemAddr1,MemAddr2;
input [31:0] InData;
output [31:0] OutData;
reg [31:0] membank [127:0];
reg [31:0] data;
assign OutData = (Oen == 1'b1) ? data : 16'bz;
always@(posedge clk)
begin
if(RdWr0_1)
data <= membank[{1'b0,MemAddr2}];
else
membank[{1'b0,MemAddr1}] <= InData;
if(RdWr0_2)
data <= membank[{1'b1,MemAddr2}];
else
membank[{1'b1,MemAddr1}] <= InData;
end
endmodule
--------------------------------------------------End
Code-------------------------------------------
Thnx in advance
Apurva
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