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Message
From: Lars Segerlund<lars.segerlund@c...>
Date: Fri Mar 4 14:34:30 CET 2005
Subject: [oc] a bit of newbie advice ..
Thanks again,
This does the trick.
/ regards, Lars Segerlund.
On Wed, 2 Mar 2005 22:44:20 +0100
mrussell@d... wrote:
> Hi Lars,
> Assuming your design has close to a 50% duty cycle on your 28Mhz
> clock source and your system doesn't care about jitter in the 8Mhz
> clock you could try something like this...
>
> Generate two 4 Mhz clocks by dividing the 28Mhz by 7. One clock is
> generated on the positive edge of the clock and the other on the
> negative edge. You would then or the two clocks togethor to generate
> the 8Mhz clock.
>
> Here's some VHDL code that shows my solution...
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.NUMERIC_STD.ALL;
>
> entity clk28to8 is
> Port ( clk28 : in std_logic;
> resetn : in std_logic;
> clk8 : out std_logic
> );
> end clk28to8;
>
> architecture RTL of clk28to8 is
> signal clk8pos : std_logic;
> signal clk8neg : std_logic;
> begin
>
> -- Or two outputs to generate clock
> clk8 <= clk8pos or clk8neg;
>
> -- create the positive edge pulse
> -- This divides the 28 Mhz input by 7 to generate a 4Mhz clock
> -- The rising edge of the 28 Mhz clock is used
> process ( clk28, resetn )
> variable pos_cnt : unsigned(2 downto 0);
> begin
> if resetn = '0' then
> clk8pos <= '0';
> pos_cnt := (others => '0' );
> elsif clk28'event and clk28 = '1' then
> if pos_cnt = 1 or pos_cnt = 2 then
> pos_cnt := pos_cnt + 1;
> clk8pos <= '1';
> elsif pos_cnt < 6 then
> pos_cnt := pos_cnt + 1;
> clk8pos <= '0';
> else
> pos_cnt := (others => '0' );
> clk8pos <= '0';
> end if;
> end if;
> end process;
>
> -- create the negative edge pulse
> -- This divides the 28 Mhz input by 7 to generate a 4Mhz clock
> -- The falling edge of the 28 Mhz clock is used
> process ( clk28, resetn )
> variable neg_cnt : unsigned(2 downto 0);
> begin
> if resetn = '0' then
> clk8neg <= '0';
> neg_cnt := (others => '0' );
> elsif clk28'event and clk28 = '0' then
> -- use the positive clock to sync the negative edge of the
> clock
> if clk8pos = '1' then
> neg_cnt := (others => '0' );
> clk8neg <= '0';
> elsif neg_cnt = 1 or neg_cnt = 2 then
> neg_cnt := neg_cnt + 1;
> clk8neg <= '1';
> elsif neg_cnt < 6 then
> neg_cnt := neg_cnt + 1;
> clk8neg <= '0';
> else
> neg_cnt := (others => '0' );
> clk8neg <= '0';
> end if;
> end if;
> end process;
>
> end RTL;
>
>
> ----- Original Message -----
> From: Lars Segerlund<lars.segerlund@c...>
> To:
> Date: Wed Mar 2 17:25:34 CET 2005
> Subject: [oc] a bit of newbie advice ..
>
> > Hi,
> > I'm a bit new to verilog and I have the situation where I want to
> > generate a clock
> > from a clock available on the board, however the ratio is 3.5:1
> > i.e. I want a
> > 8 MHz clock from a 28MHz clock source.
> > Does anybody have any hint's or pointers in the right direction ?
> > Right now I am thinking of adding a secondary clock source, but I
> > would be glad if
> > I could avoid it :-) .
> > / regards, Lars Segerlund
> >
> >
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
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