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Message
From: Colin Bathe<colin.opencores.cores@s...>
Date: Wed Mar 2 18:19:19 CET 2005
Subject: [oc] a bit of newbie advice ..
You can achieve this using combinatorial logic with feedback.Basically you need to produce a state machine which changes state on both
clock edges but doesn't use clocked registers to achieve this (as most
registers will only clock on one edge). In your design you have to very
careful about race conditions as they can stop the whole thing from working.
If you can do a search on OpenCores (it wasn't working for me) I posted the
code for a divide by 1.5 clock I think some time ago.
If that isn't enough to get you going then post again and I'll think on your
problem some more. It is solvable though.
Colin
> I'm a bit new to verilog and I have the situation where I want
> to generate a clock
> from a clock available on the board, however the ratio is 3.5:1
> i.e. I want a
> 8 MHz clock from a 28MHz clock source.
>
> Does anybody have any hint's or pointers in the right direction ?
>
> Right now I am thinking of adding a secondary clock source, but
> I would be glad if
> I could avoid it :-) .
>
> / regards, Lars Segerlund
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