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Message
From: Richard Herveille<richard@h...>
Date: Sun Feb 27 10:15:32 CET 2005
Subject: [oc] I2C Core RTL Simulation / FPGA mismatch...
Hi Jeff,
> if (wb_wacc)
> case (wb_adr_i) // synopsys full_case parallel_case
> 3'b000 : prer [ 7:0] <= #1 wb_dat_i;
> 3'b001 : prer [15:8] <= #1 wb_dat_i;
> 3'b010 : ctr <= #1 wb_dat_i;
> 3'b011 : txr <= #1 wb_dat_i;
> endcase
>
> Does the // synopsys full_case parallel_case not tell the
> synthesis tool that ALL the cases are listed? All other
> cases are considered "don't care" by the synthesis tool, right?
Sorta.
>
> The "cr" register is mapped at address 3'b100. This case is
> not listed in the case statment, so this bit is optimized
> away and is not considered important.
>
> That's the problem... now when address 3'b100 is written, the
> case statement sees it as 3'bx00 and the prer(7:0) is written
> as well as cr.
You're right. I fixed it and uploaded a new version.
I also fixed the scl/sda delay issue in the testbench.
> Does the case statement not need a default line which keeps
> the previous values for the 4 registers? Am I
> misunderstanding this concept?
You either use the full_case statement, or you add a default statement.
In this case we need the default statement.
Please download the latest version from OpenCores.
Cheers,
Richard
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