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Message
From: Mike Delaney<mmdst23@g...>
Date: Fri Jan 21 18:37:04 CET 2005
Subject: [oc] Is there any alternative method to synthesise codes using
math_real?
I'd say adding a processor is going to be harder/slower then trying to
get some sort of FPU.
What kind of area requirements are you looking at? And did you look
at the Verilog FPU core?
An altenative is a new VHDL draft standard with synthesizable floating
point support. I did not have much luck getting it to work, but a lot
of the issues I had were just related to figureing out the tools (this
was early in the semester). It was VHDL-FP or FP-VHDL, Google can
definitly find it, as would a search of the FPGA and VHDL newsgroups.
Mike
On Fri, 21 Jan 2005 12:20:01 -0300, Andrés Trapanotto
<andres_t@i...> wrote:
> rishadh@y... escribió:
>
> >Respected sir(s)/ madam(s),
> >
> >I am a final year student working on a project on FFT. Since my inputs &
> >twiddle factors require the use of math_real library, I used it & was
> >succesful in simulating it.
> >
> >But, can you tell me how I can synthesise my code?
> >
> >
> >
> Perhaps you can change a little bit your design, adding a processor
> and then doing the math operations on it :)
>
> --
> Técnico Andrés Trapanotto
> INSTITUTO NACIONAL DE TECNOLOGÍA INDUSTRIAL
> Centro de Investigación Telecomunicaciones, Electrónica e Informática
> Teléfono (54 11) 4724 6300 Interno 6362
> andres_t@i...
> ___________________________________________
> 0800 444 4004 | www.inti.gov.ar
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
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