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From: tc27 at shaw.ca<tc27@s...>
Date: Fri Dec 31 13:09:20 CET 2004
Subject: [oc] RS232 WB Controller freezes on Xilinx FPGA
> Loads. You haven't really told us anything. Are you simulating, or
> running on real hardware? If you haven't simulated, then go back
> and do so.

I'm running it on a Memec Spartan2 200 - 6 board that has a MAX232
type part that converts the levels.

> What's on your device? Is it just the RS232 and GPIO? Are these
> cores
> tested and known to work?

The GPIO core looks good, its recent, and very nicely written. The
RS232 Wishbone Controller is a bit old, and not as neatly written.

> BTW, if you haven't got a very good reason not to, then use a
> global
> clock line. Why are you considering using local clocks?

At first having local clocks actually improved the stability of the
core substantually. But after another couple days, I've determined
that whether its stable or not, completely depends on the synthesis.
Like I said before I'm dividing 100 Mhz by 4 to get a system clock of
25Mhz that is clocking everything inside the FPGA.

At first I did this using one of the Xilinx DLLs, but I noticed
freezing, and thinking that it could be the DLL (or atleast my
implementation of the divider) I switched to a counter to divide the
clock. The first time I syntesized, Xilinx's ISE didnt make the
output a global clock, but everything ran fine. Later I went back and
made it a global clock, but then the RS232 core started freezing.

I did a few tests, then went back to the DLL as a divider (with global
clock output), and it stopped freezing, and worked just fine. Then I
changed a few minor things in my overall design, and it started
freezing again.

I should point out that the RS232 core freezes without asking it to do
any WISHBONE bus transactions. I simply reset the FPGA, hit <ENTER>
and the RS232 core gives me the prompt. Then I keep hitting <ENTER>
(or hold it down) and within a minute it will freeze.

Again, sometimes it will synthesize fine, and will run for hours.
Sometimes ISE synthesizes it in such a way that it freezes within a
minute. Thats why its kinda puzzling me.

Anyways I've moved on and excepted that it freezes, since its only
there for testing purposes. I'm now adding the PCI WISHBONE Bridge as
a guest, and another slave ( the Timer/Counter core ), and using
CONBUS to connect them all.

Thank you all,
Mark