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Message
From: tc27 at shaw.ca<tc27@s...>
Date: Wed Dec 29 13:28:14 CET 2004
Subject: [oc] RS232 WB Controller freezes on Xilinx FPGA
Hi, I'm running the RS232 WB controller core as a master (without any
other masters) and its connected to the GPIO WB core. It functions
fine, but I've been noticing that it freezes. I divide a 100 Mhz
clock by 2, 4, or 16, and wether its running at 50Mhz or 6.25Mhz, the
rs232 module stops responding to serial characters usually in under a
minute.
After playing around with it all for a day or two, I've noticed that
when I clock all the components using a global CLK line on the Xilinx
FPGA, that is when it freezes. When I allow it to use a local clock
(with multiple flip flop sources) then its all stable for hours
(ofcourse the skew is really bad ~ 3ns), but it functions fine.
I was wondering if anyone else could tell me how I should next debug
this? I've only taken a single course on FPGAs and VHDL, it was
rather introductory. I think it might be something with hold times?
or setup times? I'm not sure.
I'd be happy to post my VHDL code, if its needed. I'm working on a
Memec Spartan2 200-6 PCI board. Dont know if there is anything else I
can say about my problem.
Thank you for any help,
Mark
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