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Message
From: Rudolf Usselmann<rudi@a...>
Date: Fri Dec 17 15:31:56 CET 2004
Subject: [oc] truth tables in VHDL
On Fri, 2004-12-17 at 20:09, sergio@k... wrote:
> As part of my graduate paper, I'm analysing optimization of truth tables
> in RTL and it's impact on circuit size and performance. For that I ned to
> either make up or use existing RTL, preferably VHDL, with non-optimized
> truth table, medium size. I was trying to find some state machines on
> this site and others, but I was unsuccesful. Please contact me if you
> konw of some RTL that I could use.
>
> Sergio
You where unsuccessfully to find state machines on this site ?!?!?!
You have obviously not downloaded a single project and want
others to the work for you, thats disgusting ...
rudi
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Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis
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