|
Message
From: sergio at kset.org<sergio@k...>
Date: Fri Dec 17 14:09:08 CET 2004
Subject: [oc] truth tables in VHDL
As part of my graduate paper, I'm analysing optimization of truth tables
in RTL and it's impact on circuit size and performance. For that I ned to
either make up or use existing RTL, preferably VHDL, with non-optimized
truth table, medium size. I was trying to find some state machines on
this site and others, but I was unsuccesful. Please contact me if you
konw of some RTL that I could use.
Sergio
|
 |
Browse
