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dear all,

wanderwonderus@y... wrote:
> dear all,
> 
> i've read thru Tom's CF FIR design using the Confluence software. 
> Anyone knows whether the VHDL coding is suitable for any fixed point 
> and sign input or it's just limited to the unsign binary?
> 
> Besides,can i have further details on the vhdl coding for example the 
> procedure of the coding?I will be much appreciated if you could provide 
> further reading material on the design.

Hi Esther,

The core was generated with the following Confluence design.  The syntax 
is a bit out of date, but at only 20 lines of code, it would take all of 
5 minutes it bring it inline with the latest version of Confluence. 
James Gilb has a good table in the documentation comparing pre and post 
0.9 syntax.

Looking at the MultiplierBank, it appears I used unsigned multipliers. 
Drop in '*+' if you need signed.  Or better yet, make the multiplier 
operation an input to the FirFilter, so it can be parameterized.

For the latest Confluence compiler:

   http://www.confluent.org/

-Tom

component FirFilter +FilterReset +Coefficients +FilterInput 
-FilterOutput with DelayTaps MultResults is
   {Reset FilterReset {DelayBank (length Coefficients) FilterInput 
DelayTaps}}
   {MultiplierBank Coefficients DelayTaps MultResults}
   {AdderTree MultResults FilterOutput}
end

component DelayBank +NumberOfTaps +BankInput -BankOutputs is
   if NumberOfTaps == 0
     BankOutputs <- []
   else with NextTap is
     {Delay 1 BankInput NextTap}
     BankOutputs <- NextTap :: {DelayBank (NumberOfTaps - 1) NextTap $}
   end
end

component MultiplierBank +SignalsA +SignalsB -Results is
   {Map2 (comp +A +B -X is {Delay 1 (A '*' B) X} end) SignalsA SignalsB 
Results}
end

component AdderTree +Signals -Result with BinOp UnOp is
   component BinOp +A +B -X is {Delay 1 (('msb' A '++' A) '+' ('msb' B 
'++' B)) X} end
   component UnOp  +A    -X is {Delay 1  ('msb' A '++' A) X} end
   {Tree BinOp UnOp Signals Result}
end

> 
> Thanks,
> Esther
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