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Message
From: Richard Herveille<richard@h...>
Date: Tue Dec 7 08:31:57 CET 2004
Subject: [oc] Wishbone interface between two devices
Let's continue on your example, the ethernet MAC.
The ethernet MAC has a wishbone bus, it has been used and extensively tested
with this bus.
So you do not want to touch this, unless you have a very profound reason.
In your case the simplest solution is to create a new IP core with two
ports; the microprocessor bus, and a wishbone bus. This IP core bridges the
wishbone bus to the microprocessor bus; hence the naming "bridges" for this
type of IP.
So the basic operation is as follows, the microprocessor asserts signals on
its bus, the bridge translates these into wishbone signals, and the ethernet
MAC responds to these. Any signals from the ethernet MAC enter the bridge,
are translated to signals on the microprocessor bus, and the mcu responds to
these.
There are a couple of examples for different types of microprocessor to
wishbone bridges on OpenCores (motorola coldfire, TI dsp, etc).
Hope this helps,
Richard
> -----Original Message-----
> From: cores-bounces@o...
> [mailto:cores-bounces@o...] On Behalf Of bumkele@y...
> Sent: Wednesday, December 01, 2004 3:24 PM
> To: cores@o...
> Subject: [oc] Wishbone interface between two devices
>
> Hello
>
> I have seen that the majority of the available IP cores are
> using the wishbone interface.
> But I must implement an ethernet MAC core (for example) in a
> FPGA with an external microprocessor. In fact, I only have a
> standard memory interface between my FPGA and the Microprocessor.
>
> Is the Wishbone interface usable and How to interface the two
> components?
>
> Thanks
>
> Bumkele
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
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