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Message
From: Igor Mohor<igor.mohor@g...>
Date: Tue Dec 7 08:39:02 CET 2004
Subject: [oc] Wishbone interface between two devices
You'll need to add something to bridge WB interface to your memory
interface or you can change the eth_wishbone.v module. WB is pretty
simple bus, find more details about it on the opencores website.
Regards,
Igor
On Wed, 1 Dec 2004 15:24:17 +0100, bumkele@y... <bumkele@y...> wrote:
> Hello
>
> I have seen that the majority of the available IP cores are using the
> wishbone interface.
> But I must implement an ethernet MAC core (for example) in a FPGA
> with an external microprocessor. In fact, I only have a standard
> memory interface between my FPGA and the Microprocessor.
>
> Is the Wishbone interface usable and How to interface the two components?
>
> Thanks
>
> Bumkele
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
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