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Message
From: Colin Bathe<colin.opencores.cores@s...>
Date: Fri Oct 15 13:03:56 CEST 2004
Subject: [oc] Frequency divider
Easy question of the day.Set the DPLL to produce a multiple of 2.048MHz and then divide this clock
down to produce the 2.048MHz.
> Hi
>
> I'm working with the NIOS I and i need to generate a 2.048Mhz digital
> clock. i cant get the pll's to go bellow 15MHZ.
>
> how else can i acurately get 2.048MHz ???
>
> thanks
> thinus
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