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Hi,

Hi Edmond,
I'm new to this myself, but you can find examples of how to
implement Wishbone cycles in VHDL in some of the VHDL cores
on the OpenCores website, e.g. the I2C controller.
I don't think there is an official reference on how to implement
Wishbone cores in VHDL.

This is the approach I've been using, with a very simple toy
example below:
 >>
process(wb_rst_i, wb_clk_i, wb_cyc_i, wb_stb_i)

   type state_type is { idle, reading, done);
   variable state : state_type;

begin
   if (wb_rst_i = '1') then
     <do initialisation here>
      state := idle;
   elsif (rising_edge(wb_clk_i)) then
     case (state) =>
       when idle =>
         if (wb_cyc_i = '1') then
           state := reading;
          end if;
       when reading =>
         wb_ack_o <= wb_stb_i;
         if (wb_cyc_o = '0') then
           state := idle;
         elsif (wb_stb_i = '1') then
           some_signal <= wb_dat_i;
         end if;
       when others => null;
     end case;
   end if;
end process;
 >>
I'm not sure what you think is messy about the behavioural state-machine
approach; it seems straightforward to me.
The tool I use (Altera's Quartus) runs a timing-analyzer after synthesis
and warns me whenever timing requirements aren't met and shows the
critical paths. So I can either clock the circuit slower or cut the path
with registers.

But I am also a beginner, so maybe something about the above is bad
practise, and other VHDL gurus can speak up and correct me.

Hope this helps,
Paul

Edmond Cote wrote:

> Hi,
> 
> I'm curious to know in what fashion bus cycles should
> be implemented in VHDL, specifically using the
> WISHBONE bus system.
> 
> Describing these cycles behaviorally (wait statements)
> seems to be the logical solution, however the code
> would not be synthesizable (or would it be with newer
> tools?, if so which ones?).
> 
> Likewise, how would one deal with timing issues (setup
> time/hold time) when dealing with this problem.
> 
> Is the solution to these above two problems simply to
> write tedious state machines (mealy or moore?) and
> counters (for the timing), or is there hopefully a
> more efficient way?
> 
> Can anyone suggest some references?
> 
> Thanks in advance!
> 
> Edmond
> 
> 
> 
> 
> 		
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