|
Message
From: Edmond Cote<edmond_cote@y...>
Date: Tue Aug 31 15:35:28 CEST 2004
Subject: [oc] VHDL bus cycle implementation for wishbone/opencores
Hi,I'm curious to know in what fashion bus cycles should
be implemented in VHDL, specifically using the
WISHBONE bus system.
Describing these cycles behaviorally (wait statements)
seems to be the logical solution, however the code
would not be synthesizable (or would it be with newer
tools?, if so which ones?).
Likewise, how would one deal with timing issues (setup
time/hold time) when dealing with this problem.
Is the solution to these above two problems simply to
write tedious state machines (mealy or moore?) and
counters (for the timing), or is there hopefully a
more efficient way?
Can anyone suggest some references?
Thanks in advance!
Edmond
_______________________________
Do you Yahoo!?
Win 1 of 4,000 free domain names from Yahoo! Enter now.
http://promotions.yahoo.com/goldrush
|
 |
Browse
