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    Navigation: All forums > Cores > Message List > Message Post

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    From: Marko Mlinar<markom@f...>
    Date: Wed Aug 25 10:49:21 CEST 2004
    Subject: [oc] Parallel Array Processor Project
    Top
    Markus,

    Your project is so called medium-grained programmable array. I would say the
    compiler flow is more similar to FPGA / synthesis.

    There is a (startup) company trying to push FPOA (field programmable object
    array) for math applications from FPGA side.
    On the other hand there is also company called PACT, which have solutions in
    this area for some time, and have also done a lot of work in parallel-C and
    stuff for their CPU arrays.

    You can see that latest observations are not new and are one of three ways to
    go in the future (fine, medium and large grained arrays).

    The architecture really depends on the problem you are trying to solve. So far
    multiprocessor arrays with fast CPUs have proven best for more sequential
    problems and FPGAs have proven best for massive parallel applications.

    best regards,
    Marko

    On Tuesday 24 August 2004 13:25, markus@r... wrote:
    > Question was: "Isn't the PM an FPGA? What are the differences between
    > those?"
    >
    > I thought this somewhat hard at yesterday evening, but I haven't yet
    > found any good answers. The fact is: The PM can be implemented using
    > FPGA, and if I ever reach that point, it's implemented using FPGA.
    >
    > So, for FPGA point of view, PM is just one CPU core amongst the others.
    > But I'll keep thinking a little bit about the common features and
    > differences between these two.
    >
    > In the meantime, I'll continue the development :-)
    >
    > ---
    >
    > > If I describe the PM cell in the same way, I would write: "A
    > > PM cell basically consists of an ALU with two 8-bit inputs
    > > and one 8-bit output."
    >
    > This was a little bit wrong - the cell has N inputs (N >= 3), and the
    > internal processing unit has two inputs (selected from the neighbor
    > results).
    >
    > > For real world implementations, the one ALU is shared amongst
    > > multiple
    > > cells (in other words, ALU may have more than two inputs and one
    > > output), with some additional hardware for accelerating."
    >
    > And here, the ALU doesn't have more than two inputs, but the so called
    > macrocell can have.
    >
    > ---
    > I wrote a short initial PDF of the abstract hardware model of the PM:
    >
    > http://reaaliaika.net/pdfs/pm.abstract.hw.000.sxw.pdf
    >
    > ..And, of course, I wrote a short initial thoughts about the real world
    > hardware implementations:
    >
    > http://reaaliaika.net/pdfs/pm.realworld.hw.000.sxw.pdf
    > _______________________________________________
    > http://www.opencores.org/mailman/listinfo/cores



    ReferenceAuthor
    [oc] Parallel Array Processor ProjectMarkus

     
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