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Message
From: markus at reaaliaika.net<markus@r...>
Date: Tue Aug 24 13:25:55 CEST 2004
Subject: [oc] Parallel Array Processor Project
Question was: "Isn't the PM an FPGA? What are the differences between
those?"
I thought this somewhat hard at yesterday evening, but I haven't yet
found any good answers. The fact is: The PM can be implemented using
FPGA, and if I ever reach that point, it's implemented using FPGA.
So, for FPGA point of view, PM is just one CPU core amongst the others.
But I'll keep thinking a little bit about the common features and
differences between these two.
In the meantime, I'll continue the development :-)
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> If I describe the PM cell in the same way, I would write: "A
> PM cell basically consists of an ALU with two 8-bit inputs
> and one 8-bit output."
This was a little bit wrong - the cell has N inputs (N >= 3), and the
internal processing unit has two inputs (selected from the neighbor
results).
> For real world implementations, the one ALU is shared amongst
> multiple
> cells (in other words, ALU may have more than two inputs and one
> output), with some additional hardware for accelerating."
And here, the ALU doesn't have more than two inputs, but the so called
macrocell can have.
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I wrote a short initial PDF of the abstract hardware model of the PM:
http://reaaliaika.net/pdfs/pm.abstract.hw.000.sxw.pdf
..And, of course, I wrote a short initial thoughts about the real world
hardware implementations:
http://reaaliaika.net/pdfs/pm.realworld.hw.000.sxw.pdf
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