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Message
From: markus at reaaliaika.net<markus@r...>
Date: Mon Aug 23 18:12:10 CEST 2004
Subject: [oc] Parallel Array Processor Project
Below, there's replies to other postings, too.---
Gunnar:
> An FPGA cell basically consists of a look-up-table (LUT) with four
> binary inputs and one binary output. At the output there is a
> one-bit register (flip-flop). The LUT can be programmed by a
> 16-bit word (= "the program"), whose bits are the value of
> the output for the 2^4 possible combinations of the inputs.
> In reality, the basic cell of the FPGA is a little bigger,
> containing a few LUTs and flip-flops, and some multiplexers
> to allow the LUTs to be combined in different ways.
> The "program" of each LUT is normally loaded during
> boot-up configuration and then stays the same. But also see below.
>
> I guess the PM cells are at least a few bits wider, but what other
> differences are there?
If I describe the PM cell in the same way, I would write: "A PM cell
basically consists of an ALU with two 8-bit inputs and one 8-bit output.
The ALU can be programmed by a X-bit word. The result of the inputs is
calculated to result register, when the inputs are ready.
For real world implementations, the one ALU is shared amongst multiple
cells (in other words, ALU may have more than two inputs and one
output), with some additional hardware for accelerating."
One thing is, that in (current) PM model, you implement aggregate data
types using streams of bytes. I selected that approach, because it
won't need synchronizing multiple cells and it require wider ALUs for
processing large data elements.
[Program for writing programs]
> You can. If not in other ways, you can implement a traditional CPU
> in the FPGA to do it... :-)
Ah, yes, of course :-)
> I believe (without knowing) that this would also be the most
> efficient way of implementing a compiler in an FPGA.
I have been thinking the same kind of analog for the PM, too - using
interpreters for processing data. So, analoguously:
FPGA has CPU cores <==> PM has interpreters
> This shall, however, not be confused with the general abstraction
> level of VHDL (or Verilog). Only subsets of the languages are
> synthesizable (ie possible to use to describe RTL hardware). You
This was new for me, but really, I should have guessed that.
> (some kind of PDA-like thing with the possibility to run a few
> different "applications", the selected one were then loaded
> from memory into (parts of) the FPGA.
Sounds very interesting!
---
Nico:
> > One thing is sure; the FPGA has been designed to process
> > electronical signals. The PM has been designed to process
> > abstract signals - data. PM is like a FPGA, not operating
> > in the physical world, but in the abstract, virtual data world.
> > Does it make any sense?"
>
> No :)
:-(
..Allright, I'll try to invent something else :-)
> The PM is something in between. Instead of manipulating bit by bit
> as an FPGA, it could manipulate a 8 bits high speed serial link.
> Instead of using register, it use memory. Instead of using gate,
> it use an alu.
Yes, right.
> Because each pm is a cpu, you could handle very complexe controle
> structure. In the FPGA world, controle became mega udge FSM... so
> udge that some time a embedded cpu + a ROM is smaller and faster.
It's extremely hard, if not impossible, to beat the CPU+memory
architecture in the compactness. I wouldn't even try to do that.
> I don't know if it's better than your array look like a cpu (but
> very hard to programm) or an FPGA (not supposed to
> reprogram it-self).
You're certainly right here!
This makes my project even harder. To be successful:
* It should be easy to program :-)
* It should beat FPGA in the data processing areas, that is, the cell
processor should be tighter than implementing the same logic with FPGA
* It should beat conventional processors in the performance of
computing
I'll try to encourage myself to try it...
> Maybe you should look at the code of ghdl.free.fr (it's vhdl
> simulator) to look how synthetiser extract the hardware
> description langage to map it to an FPGA.
I will certainly do that!
> An cpu array compiler will look at "task block" or map
> the content of a vhdl process in it, directly.
I have thought, that the compiler will output microcode programs for
cells, thus mapping certain sequential processes directly for the
sequential cell processor.
[reading the state of the FPGA]
> Yep, throught the boundary scan controlled by the JTAG interface.
> It's mainly use for Fab testing.
Oops, I totally forget this!
> > Would you believe, that I already have thought of having these
> > kind of "buses" inside the array (something like a built-in serial
> > interface or network)?
>
> not bus ! message passing, lan, but not bus that require an answer.
Sorry, I'm not very familiar with the terminology.
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