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Message
From: nico at seul.org<nico@s...>
Date: Mon Aug 23 16:00:22 CEST 2004
Subject: [oc] Parallel Array Processor Project
> Gunnar Dahlgren:
>
>> Isn't it so that your architecture actually IS the architecture
>> of an FPGA? Or very much like it anyway [...]
>
> I added the comment with my reply to my web pages (feedback
> section), because it just brought a whole new world in to my mind...
>
> I also thought the issue a little further and made this addition:
>
> "What really is the difference between the PM and the FPGA? I must
> think more about this, because it could reveal some extraordinary
> possibilities for the PM.
>
> One thing is sure; the FPGA has been designed to process electronical
> signals. The PM has been designed to process abstract signals - data.
> PM is like a FPGA, not operating in the physical world, but in the
> abstract, virtual data world. Does it make any sense?"
No :)
FPGA only manipulate one and zero. When you aggregate them, bit means
data, or abstracte data.
Do you remember of the coding paradigm : "intelligence must be in the
data". Software code is the data of the HW.
It's possible to put intelligence in hardware but it's more costly than
put it in "DATA", the software.
The PM is something in between. Instead of manipulating bit by bit as an
FPGA, it could manipulate a 8 bits high speed serial link. Instead of
using register, it use memory. Instead of using gate, it use an alu.
Because each pm is a cpu, you could handle very complexe controle
structure. In the FPGA world, controle became mega udge FSM... so udge
that some time a embedded cpu + a ROM is smaller and faster.
I don't know if it's better than your array look like a cpu (but very hard
to programm) or an FPGA (not supposed to reprogram it-self). This is
something in between at least for the kind of application. I imagine that
complexe and heavy data manipulation task could use it (as MPEG 4 codeur).
Maybe you should look at the code of ghdl.free.fr (it's vhdl simulator) to
look how synthetiser extract the hardware description langage to map it to
an FPGA. This synthetiseurs try to find known bloc : FSM, counter, ...
An cpu array compiler will look at "task block" or map the content of a
vhdl process in it, directly.
Nicolas Boulay
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