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Message
From: markus at reaaliaika.net<markus@r...>
Date: Mon Aug 16 17:20:08 CEST 2004
Subject: [oc] Parallel Array Processor Project
> i read : "How about running redesigned 80486 with 2.8GHz clock
> and having one hundred of those serving your applications? "
>
> Be carefull !! A 468 with today technology should run about 200/400
> Mhz even less ! What make the difference between P4 and 486
> is 20 (and now 40) pipestages.
That's why the word "redesigned" ;-) As we all know, the main reasons
for the higher processor clock frequencies are new faster transistors
and increased pipelines.
But a simple processor core should be able to be clocked with higher
frequency than a 40-stage pipelined P4. And, if the cell data width is
kept in 8-bits, it should be faster than it's 32/64-bit cousins.
> The 122 Millions transistor chip of ATI (x800) run around 350 Mhz.
Yes, if the data paths inside the chip are long, you can't get high clock
frequencies.
[programming languages]
> I have heard about C + extention to use the paradigm of uniform
> memory adressing.
Yes, they do that too.
[cell arrays]
> > The array itself contains the code - a single cell contains
> > only the instruction it will execute, when fired.
>
> So you will need a very very fast network to provide instruction to
> each cell:/
I didn't quite follow this... Yes and no I need fast connections.
The cells have an internal memory location to store the instruction,
which is executed. During execution, it's not fetched from anywhere.
My virtual memory plans requires a huge bandwidth (or let's say, that
bandwidth would help a lot), when the cell number increases - but when
there's enough cells, it's not needed anymore. And, meantime you can
have many different virtual memory hierarchies to overcome the
bandwidth problem.
All in all, virtual memory requires as much bandwidth as in conventional
processors, not more, not less.
> I beleive you will have the same problem than place & route
> tools for ASIC/FPGA : some time some data should be provide
> to hundred of cell and that could consume a lot of cell just
> for routing.
Exactly! The basic model is not optimal for SIMD-style processing,
because data propagation reserves numbers of cells and it's not
propagated "immediately" (but it will grantly flow inside the array).
The basic model is better suited for pipelined processing (vector
programming).
> Some data replication/modification propagation
> model should be used :)
If you want to save cells (as we probably want), yes. If you have
enough of them (in the future), why bother? ;-)
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