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Message
From: markus at reaaliaika.net<markus@r...>
Date: Mon Aug 16 15:35:30 CEST 2004
Subject: [oc] Parallel Array Processor Project
> > That's why I have borrowed many things from VHDL to my HLL.
> >
> Why yet a new langage ?
There's not many programming languages, which support low-level, fine-
grained parallelism. Many of them are hard to be used for general
purpose programming (e.g. APL) or they are based on sequential
constructions (LISP, Prolog). The most usable programming languages
are sequential (C, Pascal and alikes).
[MatrioshkaBrains]
> > > I think the best model is a PC cluster. Every node contain
> > > memory
> > > and is linked to the closest other cell. Then the routing
> > > algorithm could be fractal like.
> >
> > Well, my design principles are:
> >
> > * Every node contain a memory - at least one single 8-bit
> > result and an instruction.
>
> If it's lsome tiny cpu programmed like macro-cell of FPGA are, it
> must also contain all the memory code.
The array itself contains the code - a single cell contains only the
instruction it will execute, when fired.
> > * Neighborhood connection: The ways to route data to distant
> > cells is up to the software.
>
> So local node decide the route to an other cell.
Yes.
> That's not the TCP/IP moto :/ The local node must be aware
> of the topology of the local connection.
Well, the local node need only to move data from it's input to it's result.
With the software you construct more complex routing.
> It could be really hard to make a fast routing.
True. That's why I have thought of having hardware accelerators for
special purposes, like long distance data transfers. But hardware
acceleration solutions are not scalable and thus they can be applied
only for specific size of the array. That's why the fundamental model
doesn't contain them (they are used only for HW implementations).
For real world implementation, I have thought of having a hierarchial
structure of the array. That means, that at the bottom, there's a
processor core executing the cell instructions. They form a larger unit,
and connecting these larger units you form even larger units.
But I have somewhat covered those issues on my web site.
> > The normal PC clusters are often topologically stars (central
> > control) or
> > full-connected (each node can contact any node in the
> > cluster).
>
> http://aggregate.org/KLAT2/ describe an other topology much more
> efficient and scalable.
Well, yes, that's one possible hardware topology. In my design I'm still
quite sceptic to use any other than neighborhood connections, for the
reasons I described above.
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