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Message
From: kavi<nkavv@s...>
Date: Mon Aug 16 14:32:32 CEST 2004
Subject: [oc] Parallel Array Processor Project
----- Original Message -----
From: <markus@r...>
To: <cores@o...>
Sent: Monday, August 16, 2004 2:55 PM
Subject: Re: [oc] Parallel Array Processor Project
> > markus@r... wrote:
> > > My area of intrest is MIMD and I'm very aware, that the
> > > architecture I'm currently planning won't beat SIMD-processors
> > > or systolic arrays in their strong area. That's not a target for
> > > the project; the target is to design architecture and tools
> > > for general purpose parallel processor.
It is seems you clarify your application field and your expectactions.
Agree.
--
I don't have strong background on processor systems of MIMD-granularity, but
i will comment on the following:
> But, most of you are probably familiar with VHDL - that's one of the
> existing parallel languages and you probably know, that it's not
> impossible to make something usable with it, and it's even possible to
> make the code somewhat understandable, too.
Well, VHDL does not adhere to any programming model! It is not a programming
language, but a hardware description language, that mistake is coming up
every week or so. In an HDL you just get to describe module connectivity and
their internal functionalities. Of course, the VHDL notion of an event and
the ability of parallel process execution (parallel in simulation time
advancing) is necessary to model hardware.
> [PicBlaze/KCPSM]
> > For your neural network experiments, I believe that type of
> > implementation should suffice. Implementing a perceptron should
> > not take too many instructions.
I think that neural nets on hardware need some more specific programmer's
model. It sounds reasonable to have custom memory organization with some
data structures (as constant or non-constant coefficients) allocated in
scratchpad RAM, careful design of the memory interface, and maybe a
coarse-grain unit in the execution stage for the given topology of the NN.
The Picoblaze solution is OK if you can't spare time, need something better
verified with software tools or either way could much your performance
requirements. I don't expect a specialized processor for NN emulation will
map efficiently on the fine-grain FPGAs. It depends on your application
characteristics, too.
Nikolaos Kavvadias
nkavv[at]skiathos.physics.auth.gr
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