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Message
From: Joachim Strömbergson<Joachim.Strombergson@I...>
Date: Thu Jul 15 11:33:07 CEST 2004
Subject: [oc] Parallel Array Processor Project
Aloha!markus@r... wrote:
>>The Raw project is here:
>>http://www.cag.lcs.mit.edu/raw/
>
>
> OK, I read the available information of RAW, Transit, iRAM and those.
>
> RAW is "regular" transputer -like architecture. The similarities between
> these architectures and mine is the connection network (just ot
> neighbors) and for the same reasons - this kind of network is highly
> scalable compared to any central-controlled networks.
>
> The difference between my project and these "transputer" -like
> architectures are the cell design. Both transputer and MIT RAW use
> quite regular CPUs as processing nodes. I'm trying to construct an
> independent cell, which have:
The RAW processing element is quite simplistic. But, my recommendation at
looking at Raw for inspiration was to see a research project that:
(A) Have developed massive PE-arrays on chip.
(B) Have worked a lot on the SW-aspect. Something I think you will consider
quite a bit.
There are others too. And mabye for you SIMD-like systems with small PEs are
more appropriate. MITs Transit project (which I mentioned too) contains lots
of interesting tidbits on this, for example:
http://www.cs.caltech.edu/research/ic/transit/tn95/tn95.html
AFAIK Transit is dead and a few years old, but still interesting to check out.
BTW: I found this posting at fpgacpu.org interesting:
http://www.fpgacpu.org/usenet/array.html
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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