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Message
From: markus at reaaliaika.net<markus@r...>
Date: Wed Jul 14 16:51:19 CEST 2004
Subject: [oc] Parallel Array Processor Project
> I've implemented a very simple 16 bit microprocessor and I figure I
> can fit 8 of them in the XC2S300e.
> http://members.optushome.com.au/jekent/Micro16Array/index.html
I took a look of your design (I'll study it more closely later). We have
one difference in fundamentals: in my model, processors can change
only their own state (i.e. memory), they have read-only access to the
states (memory) of the neighbor. I selected this approach as the base
of the design to overcome the difficultiness in concurrent writes (i.e.
multiport RAM cells).
> I was going to use my VHDL 6809 clone core to control the processor
> array from a separate board but had a few problems working out the
> clock sharing between the boards.
Here's another difference in fundamentals: I'm trying to achieve a stand-
alone architecture, with no need for controlling devices (others than a
normal CPU have).
> logic.... but sort of lost interest as I could see no real use for
> it, and was getting a bit sick of CPU design.
You said it ;-) One possible future of my project.
> I'm not sure what scale you are interested in designing on, what
> size chips and how many.
Currently, I'm just scetching the fundamental needs for cells, which
could be used to construct that processor "cube". I must say, that I'm
a little bit sceptic, if the 2-layer "cube" would give anything new you
haven't seen already. I place my hopes to future IC manufacturing
technologies... :-)
But there's a small hope, that some of the hardware implementation
alternatives could really be a platform to implement a real, functional
and useful processor (altought that probably requires a huge amount of
gates; something like 20 million). In my dreams this kind of useful
processor would be a "parallel co-processor" in a PCI board. To go
further, if it's possible to get a Pentium-compatible pin layout and
replace the old PC's processor with a parallel one, that would be much
more interesting... But the way to go there is long.
> My budget only supports simple 300K gate devices and free web pack
> software.
I'm not yet looking a physical implementation, software simulations are
more than enough. But I could really benefit for a VHDL-models of cell
implementations.
> You might also consider what you can do with 2D and 3D cellular
> automata designs.
Yes, this was the "magic word" I'd forgot! Thanks, I'll go to the web to
search more information.
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