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Message
From: markus at reaaliaika.net<markus@r...>
Date: Wed Jul 14 16:25:44 CEST 2004
Subject: [oc] Parallel Array Processor Project
> One project you should check out is the Raw project. The Raw
> architecture is very much what you have been thinking about:
> Lots of small processing elements connected on-die.
> They have produced real chips and have done quite a lot of
> work on the non-trivial aspect of programming the beast.
Alright, I'll take a look on that. Unfortunately I wasn't able to open the
link you gave in your following posting, but I'll use google to find the
project. Thanks for the other links, too.
> I took a look at your page, and unless I'm fooled by the
> PovRay-images, you are thinking in terms if a 3D-array, no?
No, you're not fooled - the fundamental approach is to use a 3D array,
a "cube" of cells.
> If you are I think you should try to keep that 3D-thingy shallow.
> Eveb though state of the art technologies
> provides 10+ metal layers it still don't provide very much in terms
> of a third connectivity dimension. And, besides the functionality is still
> implemented at the bottom of the chip.
I know this and I write something about it in the chapter "Cell Array
Organization". I have no formal proof, but my intuition says that
two "layers" (while using 3D model) is the absolute minimum to get the
thing working - and fortunately it's quite easy to design those two
layers with one transistor layer (i.e. using current IC processes). Of
course, it's possible to use just one layer, but you have to have
crossovers in it (shown in the last example there) - or
special "crossover" instruction in the cell.
This intuition comes from the fact, that the electronic designs can still
be drawn to one sheet of paper and that 2-layer PCB can be used for
implement almost anything, if just the ICs are provided in DIP
packages...
---
But besides of this, I'm not sure, if the 2D layout could ever give
reasonable results for the cell array for two reasons - first, it can be so
that one transistor layer is just not enough to carry enough cells to get
real benefits of parallel processing, and second, it's possible that the
software compiled to 2D array has too long data transmission paths to
operate fast enough (without any hardware acceleration solutions).
So, basically I'm designing for 3D world, but I keep continuously in mind,
how to implement things with current technology.
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