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From: Praveen Durga<eeppd@b...>
Date: Wed Jul 14 15:06:14 CEST 2004
Subject: [oc] Xilinx ISE 6.2i (Linux and Windows)
Hi:

I have a querry here. I have made a small design using Aquarius
processor (opencores), single port ram (generated using Xilinx Coregen)
and some other modules.
When I implement my design using Xilinx ISE on Linux Redhat 8, nothing
works. I simulated with post-layout and post-translate simulation models
and the output fails. On linux platform, RTL simulation is passing so I
believe the problem is in synthesis of design (which uses XST).
With the same design, when I implement using Xilinx ISE on windows
platform, everything works (even my eval board).

Can someone justify this difference and give me a solution to this
issue. I really want to use Linux for development.

Thanks

Praveen Durga
SoC Research Lab
2East 2.24
University of Bath
Bath, England, UK

Follow up	Author
[oc] Xilinx ISE 6.2i (Linux and Windows)	Shawn Tan Ser Ngiap