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Message
From: bporcella<bporcella@s...>
Date: Tue Jul 13 23:56:53 CEST 2004
Subject: [oc] Generic Memories
All:In my mind a "generic" dual port memory is defined in verilog as:
reg [dw-1 :0] mem [(1<<aw) -1:0]; // instantiate memory
always @(clk) mem[wadr] <= data_in; // this is how you write
data_out = mem[radr]; // this is how you read
Specifically, the only registers associated with the "generic memory" are
those that constitute the storage array.
While I understand that to get maximum throughput from any such structure you want to
register all I/O data as "closely as possible", - there are times maximum throughput is not
needed. There are in fact design situation where multiplexors rather than registers might be more
appropriate to place near the array for maximum SYSTEM throughput.
I bring this up because Open Cores coding guidelines recommends using "generic" memories in designs
- I suppose to minimize problems in porting between FPGA technologies. While I have no
desire to cause myself extra grief, recent experience leads me to believe that
most FPGA tools can deal very nicely with a simple dual port structure like that described above.
On the other hand, my attempts to use "generic" memory in Open Cores CVS have been frustrating -- what are
described as "generic dual port rams" turn out to be "generic dual port rams with read output registers"
or "generic dual port rams with read address registers" -- or sometimes both.
I strongly suspect that most of the "generic" memories in CVS are not fully "up to date".
They are (at minimum) not well described - in my humble opinion.
Perhaps some of you who have been around awhile could think about this a few minutes.
TWO QUESTIONS
1) Are we perhaps better off using FPGA tools to instantiate memories from standard descriptions (updated often by vendors) or should we continue to try to maintain generic files that "aid" in syntheses?
2) More importantly - do the "generic" memory files we have actually aid in FPGA synthesis - if so how.?
bj Porcella
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