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Arnim,

The behavioral simulation assumes that all state transitions are
instantaneous. A successful behavioral simulation means your design
COULD work.

The timing simulation (post place and route) incorporates gate delays,
routing delays, and other timing factors. Many models that work fine in
behavioral simulations fail miserably when real-life signal timing is
simulated. That is what makes it "hard to do."

Usually, by reducing the clock rate, you can get the signals stabilized
between clock cycles so the design will work correctly. You may also
have to re-arrange your logic so that routing paths are shorter or
operations do not use signals until they have stabilized.

Steve

On Sun, 2004-07-11 at 17:55, kevinjwhite@c... wrote:
> Arnim,
> 
> Yes - you're right.  It fails with the post-place and route simulation.  I 
> hadn't done that because somebody else said it was difficult to do with 
> Modelsim...
> 
> I wonder what causes the behavioural simulation to work but the post-
> place one to fail?
> 
> thanks
> 
> kevin
> 
> ----- Original Message ----- 
> From: arniml@o...<arniml@o...> 
> To: 
> Date: Sun Jul 11 22:28:11 CEST 2004 
> Subject: [oc] C16 processor 
> 
> > Hi Kevin! 
> > 
> > > I can see that the instructions are in memory OK. Its 
> > > as if the Xilinx tools are not synthesizing the VHDL 
> > correctly. 
> > > Any hints will be welcome. 
> > Have you considered to simulate the post place & route design? 
> > ISE can 
> > write a VHDL netlist of the design after P&R and simulating it 
> > should 
> > show the same problem. I never tried this with Modelsim, maybe you 
> > have to compile some Xilinx-specific libraries. 
> > Good luck! 
> > Arnim 
> > 
> > 
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
-- 
Steven R. McQueen
McQueen Technologies, Inc.

(909) 809-3232
srmcqueen@m...