OPENCORES.ORG

I am developing a fully synthesizable 32 bit FIFO with programmable

that could be tricky.
Depends on whether it is synchronous or fallthrough,
how big it is. and what the test methodology is.

In fpga - most people forget test.
This is not a good idea  in asic or full custom.
If its smaller than (say) 1K ff's,  and synchronous, then fully 
synthesized flops is
often the best solution. Maybe full scan for test.
If its fall thru - you really want  a custom layout. You are in for a 
world of hurt if you pass
that logic to many place and route tools. For me, custom layout and 
synthesis do not sit well together.

Bigger than ~1K - you probably want a hard memory - which does not 
synthesize well.
And you get the usual set of memory test issues, probably memory bist.

These are very different solutions. I'd sugggest a small soluton , and a 
maybe big one.
john

Unmesh wrote:

> I am developing a fully synthesizable 32 bit FIFO with programmable 
> depth in verilog. AMBA APB compliance features have also been added to 
> the design. I have completed the RTL and the functional verification. 
> I need assistance w.r.t synthesizing the core ( both FPGA and 
> ASIC will do ). Assistance will be greatly appreciated.
>   Thanks and regards
>        Unmesh
>     unmesh@s...
>
>------------------------------------------------------------------------
>
>_______________________________________________
>http://www.opencores.org/mailman/listinfo/cores
>