LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Find Resources
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: John Sheahan <jrsheahan@o...>
    Date: Sun, 26 Jan 2003 10:10:27 +1100
    Subject: Re: Re: [oc] Real newbie questions
    Top

    On Sat, Jan 25, 2003 at 02:35:46PM -0000, tanveer  tan wrote:
    > !!! r there any syntheesizable testbenches??
    > 
    > 
    > tanveer
    
    Sure. 
    I worked  with quickturn emulators a while back.
    These are either arrays of FPGA's with software to spread 
    out the design, or arrays of dedicated special tiny CPUs.
    
    They are there to simulate a big design fast. 
    (close to real time)
    
    Here, the simulator running the testbench is the bottleneck.
    Using a synthesizeable testbench, together with RAM is one solution. 
    
    Its perhaps possible to argue an IC tester is another example.
    john
    
    
    

    ReferenceAuthor
    Re: Re: [oc] Real newbie questionsTanveer tan

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.