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Most popular projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) OpenRISC 1000   Updated on: 28-Sep-2008   VLM: 11412 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   Ethernet MAC 10/100 Mbps   Updated on: 24-Sep-2007   VLM: 4851 The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. This core is designed for implementation of CSMA/CD LAN in accordance with the IEEE 802.3 standards. The MAC is the portion of ethernet core ...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   USB 1.1 Host and Function IP core   Updated on: 25-Aug-2008   VLM: 3810 USB 1.1 host and function modes of operation. Full (12Mbps) and low speed (1.5Mbps) operation. Isochronous data transfers supported. Function mode supports four endpoints.   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   I2C controller core   Updated on: 09-Aug-2008   VLM: 3229 I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.   Category :: Communication controller Language :: Verilog Language :: VHDL Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   ZPU - the worlds smallest 32 bit CPU with GCC toolchain   Updated on: 23-Sep-2008   VLM: 2779 This is the worlds smallest 32 bit CPU with a GCC/GDB toolchain, operating systems support(eCos), simulator, etc. Multiple VHDL implementations available. BSD license, except for those pieces to the puzzle that already have another open so...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   10_100_1000 Mbps tri-mode ethernet MAC   Updated on: 18-Sep-2008   VLM: 2194 10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The wh...   Category :: Communication controller Language :: Verilog License :: LGPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   Plasma - most MIPS I(TM) opcodes   Updated on: 02-Sep-2008   VLM: 2152 The Plasma CPU core supports interrupts and all MIPS I(TM) user mode instructions except unaligned load and store operations.   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   CAN Protocol Controller   Updated on: 30-Apr-2008   VLM: 1896 CAN (Controller Area Network) is a widely used control network protocol. Typical Apllications are automation and in-car networking. The project aims to develop an open source implementation of CAN Protcol Version 2.0 Part A and B. It should be...   Category :: Communication controller Standard :: Wishbone compliant core Development status :: Production/Stable   8051 core   Updated on: 29-Jul-2008   VLM: 1608 The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 64K bytes of on-chip program memory.   Category :: Microprocessor Standard :: Wishbone compliant core Development status :: Alpha   USB 2.0 Function Core   Updated on: 27-Jun-2005   VLM: 1591 USB 2.0 compliant core which allows data transfers of 480 Mb/s.   Category :: Communication controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   VGA/LCD Controller   Updated on: 13-May-2004   VLM: 1576 The OpenCores VGA/LCD Controller core is a WISHBONE rev.B3 compliant embedded VGA core capable of driving CRT and LCD displays.   Category :: Video controller Language :: Verilog Phaze :: ASIC proven Phaze :: Design done Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Video compression systems   Updated on: 27-Aug-2008   VLM: 1555 The Video Systems project is a collection of readily available blocks to build different types of compression standards, like H.310, H.320, MPEG-1, MPEG-2 etc.   Category :: Video controller Development status :: Production/Stable   Zet - The x86 (IA-32) open implementation   Updated on: 06-Oct-2008   VLM: 1548 This project implements a version of the common Intel IA-32 instruction set into a commercial FPGA.   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Alpha   PCI bridge   Updated on: 04-Jul-2006   VLM: 1391 PCI bridge is a member of a family of open source cores. It is a bus bridge device, which enables access to PCI bus to other WISHBONE SoC bus compatible cores.   Category :: System controller Language :: Verilog Standard :: Wishbone compliant core Development status :: Production/Stable   AVR Core   Updated on: 30-Aug-2008   VLM: 1186 AVR core, UART, Timer/Counter and parallel ports   Category :: Microprocessor Development status :: Production/Stable