By category :: Last updated :: Last created :: Most popular :: Best rated

Last updated projects We use a few icons to help identify projects: Indicates new project, that has been added in the last 30 days. Indicates project that is ready to use Indicates a WISHBONE Compliant Core VLM = Visits Last Month (how many people accessed project) Zet - An FPGA port of the IA-32 architecture   Updated on: 07-Sep-2008   VLM: 903 This project implements a version of the common Intel IA-32 instruction set into a commercial FPGA.   Category :: Microprocessor Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Alpha   OpenRISC 1000   Updated on: 06-Sep-2008   VLM: 12157 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets ...   Category :: Microprocessor Language :: Verilog License :: LGPL Phaze :: ASIC proven Standard :: Wishbone compliant core Development status :: Production/Stable   ZPU - the worlds smallest 32 bit CPU with GCC toolchain   Updated on: 04-Sep-2008   VLM: 3074 This is the worlds smallest 32 bit CPU with a GCC/GDB toolchain, operating systems support(eCos), simulator, etc. Multiple VHDL implementations available. BSD license, except for those pieces to the puzzle that already have another open so...   Category :: Microprocessor Language :: VHDL Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Beta Development status :: Production/Stable   JOP: a Java Optimized Processor   Updated on: 03-Sep-2008   VLM: 1294 JOP is the implementation of the Java Virtual Machine (JVM) as concrete machine in hardware. The design is full synthesizable and fits in low-cost FPGA devices from Altera and Xilinx.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Bluespec SystemVerilog Reed Solomon Decoder   Updated on: 02-Sep-2008   VLM: 120 A high-performance Reed Solomon decoder written in Bluespec SystemVerilog     OpenRISC 1200 Fault Tolerant   Updated on: 02-Sep-2008   VLM: 175 a fault tolerant version of OpenRISC 1200 processor. it add modules that will protect Cache, Register file and Memory. the main goal of the project is to achive a fault-coverage of 95% with area-and-power overhead as low as possible suitable ...     Plasma - most MIPS I(TM) opcodes   Updated on: 02-Sep-2008   VLM: 1911 The Plasma CPU core supports interrupts and all MIPS I(TM) user mode instructions except unaligned load and store operations.   Category :: Microprocessor Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable   System09   Updated on: 31-Aug-2008   VLM: 444 6809 instruction compatible microprocessor core. SOC version includes UART, Compact Flash Interface, Monitor ROM Simple Video Display, PS/2 keyboard interface and 16 bytes of Dynamic Address Translation Registers   Category :: Microprocessor Category :: SoC Language :: VHDL License :: GPL Development status :: Production/Stable   AVR Core   Updated on: 30-Aug-2008   VLM: 1369 AVR core, UART, Timer/Counter and parallel ports   Category :: Microprocessor Development status :: Production/Stable   T400 µController   Updated on: 28-Aug-2008   VLM: 435 An implementation of National's COP400 4-bit microcontroller family architecture. It is intended to be used as a replacement for the original chip in SOCs recreating legacy systems.   Category :: Microprocessor Language :: VHDL License :: GPL Phaze :: Design done Phaze :: FPGA proven Development status :: Production/Stable   FIR-Gen   Updated on: 28-Aug-2008   VLM: 274 This programm generates synthesis able vhdl code from filter coefficients. The programm is written in C++.     M2G - Media Oriented Systems Transport (MOST) IP core   Updated on: 27-Aug-2008   VLM: 635 With the M2G protocol a high performance, very scalable and easy to implement multi media transport system for in car use shall be defined. Inspired by the MOST protocol (Media Oriented Systems Transport) (http://www.mostcooperation.com) but with...   Category :: Communication controller Language :: Verilog Language :: VHDL Standard :: Wishbone compliant core Development status :: Planning   Video compression systems   Updated on: 27-Aug-2008   VLM: 1811 The Video Systems project is a collection of readily available blocks to build different types of compression standards, like H.310, H.320, MPEG-1, MPEG-2 etc.   Category :: Video controller Development status :: Production/Stable   SD/MMC Controller   Updated on: 25-Aug-2008   VLM: 1206 SD (Secure Digital) and MMC memory card controller with Wishbone slave interface. Handles all aspects of card initialization, 512 byte block read, and block write. Hides the complicated SD/MMC memory interface, and presents the user with a simple...   Category :: Communication controller Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable   Kotku - The IBM PC complete system   Updated on: 25-Aug-2008   VLM: 378 This project is connected with Zet, the FPGA port of the IA-32 processor.